IP Library Assignment 054772/0918
Patent Assignment
Reel/Frame 054772/0918

Assignment of Assignor's Interest

Recorded: 2020-12-16 Pages: 17
Assignor
INTEL CORPORATION
Executed: 2020-11-13
Assignee
GOOGLE LLC
1600 AMPHITHEATRE PARKWAY, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties (64)
Memory Management Circuitry Translation Information Retreival During Debugging
Patent: 7,296,137 →
Application: 11/140,176 →
Publication: US 2006/0271759
Translation Information Retrieval Transparent to Processor Core
Patent: 7,299,335 →
Application: 11/140,310 →
Publication: US 2006/0271919
Complementary Metal Oxide Semiconductor Integrated Circuit Using Raised Source Drain and Replacement Metal Gate
Patent: 7,569,443 →
Application: 11/159,430 →
Publication: US 2006/0286729
Multigate Device with Recessed Strain Regions
Patent: 7,525,160 →
Application: 11/320,309 →
Publication: US 2007/0145487
Methods of Forming Improved Epi Fill on Narrow Isolation Bounded Source/Drain Regions and Structures Formed Thereby
Patent: 7,691,752 →
Application: 11/694,458 →
Publication: US 2008/0237742
Semiconductor Device Having Self-Aligned Epitaxial Source and Drain Extensions
Patent: 7,732,285 →
Application: 11/729,189 →
Publication: US 2008/0242037
Silicon Germanium and Germanium Multigate and Nanowire Structures for Logic and Multilevel Memory Applications
Patent: 7,821,061 →
Application: 11/729,565 →
Publication: US 2008/0237575
Mechanism for Effectively Caching Streaming and Non-Streaming Data Patterns
Patent: 8,108,614 →
Application: 11/967,413 →
Publication: US 2009/0172291
Fabrication of Germanium Nanowire Transistors
Patent: 7,727,830 →
Application: 12/006,273 →
Publication: US 2009/0170251
Power Management for Multiple Processor Cores
Patent: 8,402,290 →
Application: 12/263,421 →
Publication: US 2010/0115304
Complementary Metal Oxide Semiconductor Integrated Circuit Using Raised Source Drain and Replacement Metal Gate
Patent: 8,148,786 →
Application: 12/493,291 →
Publication: US 2009/0261391
Isolation for Nanowire Devices
Patent: 8,269,209 →
Application: 12/653,847 →
Publication: US 2011/0147697
Fabrication of Germanium Nanowire Transistors
Patent: 8,110,458 →
Application: 12/762,585 →
Publication: US 2010/0200835
Silicon Germanium and Germanium Multigate and Nanowire Structures for Logic and Multilevel Memory Applications
Patent: 8,722,478 →
Application: 12/885,071 →
Publication: US 2011/0008937
Techniques for Current Mirror Circuits
Patent: 8,188,792 →
Application: 12/889,772 →
Mechanism for Effectively Caching Streaming and Non-Streaming Data Patterns
Patent: 8,065,488 →
Application: 12/908,183 →
Publication: US 2011/0099333
Enhanced Flip Chip Package
Patent: 8,716,859 →
Application: 13/346,993 →
Publication: US 2013/0175686
Isolation for Nanowire Devices
Patent: 8,883,573 →
Application: 13/563,456 →
Publication: US 2012/0309173
Trench Confined Epitaxially Grown Device Layer(S)
Patent: 8,765,563 →
Application: 13/630,527 →
Publication: US 2014/0091360
Tin Doped Iii-V Material Contacts
Patent: 8,896,066 →
Application: 13/685,369 →
Publication: US 2013/0154016
Deep Gate-All-Around Semiconductor Device Having Germanium or Group Iii-V Active Layer
Patent: 9,136,343 →
Application: 13/749,139 →
Publication: US 2014/0203327
Chip Arrangements
Patent: 8,907,480 →
Application: 13/802,848 →
Publication: US 2014/0264832
Power Management for Multiple Processor Cores
Application: 13/847,392 →
Publication: US 2013/0219196
Iii-V Layers for N-Type and P-Type Mos Source-Drain Contacts
Patent: 9,153,583 →
Application: 13/976,074 →
Publication: US 2013/0285155
Self-Aligned Contact Metallization for Reduced Contact Resistance
Patent: 9,059,024 →
Application: 13/976,075 →
Publication: US 2013/0277752
Group Iii-N Nanowire Transistors
Patent: 9,240,410 →
Application: 13/976,413 →
Publication: US 2013/0279145
Structure having a planar bonding surface
Patent: 8,994,174 →
Application: 13/994,660 →
Publication: US 2013/0264707
Nanowire Structures Having Wrap-Around Contacts
Application: 13/995,914 →
Publication: US 2014/0209855
Nanowire Structures Having Non-Discrete Source and Drain Regions
Patent: 9,087,863 →
Application: 13/995,930 →
Publication: US 2014/0042386
Semiconductor Devices Having Modulated Nanowire Counts
Application: 13/996,505 →
Publication: US 2013/0313513
Common-Substrate Semiconductor Devices Having Nanowires or Semiconductor Bodies with Differing Material Orientation or Composition
Patent: 9,559,160 →
Application: 13/996,506 →
Publication: US 2013/0320294
Stacked Memory Allowing Variance in Device Interconnects
Patent: 9,627,357 →
Application: 13/997,152 →
Publication: US 2013/0292840
Methods to Enhance Doping Concentration in Near-Surface Layers of Semiconductors and Methods of Making Same
Patent: 9,653,559 →
Application: 13/997,166 →
Publication: US 2013/0320417
Stress Buffer Layer for Integrated Microelectromechanical Systems (Mems)
Patent: 9,056,763 →
Application: 14/039,157 →
Publication: US 2015/0091167
Enhanced Flip Chip Package
Patent: 9,059,304 →
Application: 14/164,289 →
Publication: US 2014/0138827
Silicon Germanium and Germanium Multigate and Nanowire Structures for Logic and Multilevel Memory Applications
Patent: 8,936,974 →
Application: 14/184,999 →
Publication: US 2014/0170817
Trench Confined Epitaxially Grown Device Layer(S)
Patent: 9,634,007 →
Application: 14/302,350 →
Publication: US 2014/0291726
Semiconductor Devices
Patent: 9,385,105 →
Application: 14/370,971 →
Publication: US 2015/0028478
Silicon Germanium and Germanium Multigate and Nanowire Structures for Logic and Multilevel Memory Applications
Patent: 9,343,302 →
Application: 14/571,579 →
Publication: US 2015/0099349
Method for Handling Very Thin Device Wafers
Patent: 9,252,111 →
Application: 14/625,579 →
Publication: US 2015/0162290
Stress Buffer Layer for Integrated Microelectromechanical Systems (Mems)
Patent: 9,550,670 →
Application: 14/731,211 →
Publication: US 2015/0266728
Self-Aligned Contact Metallization for Reduced Contact Resistance
Patent: 9,224,735 →
Application: 14/739,994 →
Publication: US 2015/0311204
Three Dimensional Structures Within Mold Compound
Patent: 9,711,492 →
Application: 14/778,036 →
Publication: US 2016/0358897
Nanowire Structures Having Non-Discrete Source and Drain Regions
Patent: 9,564,522 →
Application: 14/803,919 →
Publication: US 2015/0325648
Deep Gate-All-Around Semiconductor Device Having Germanium or Group Iii-V Active Layer
Patent: 9,337,291 →
Application: 14/821,561 →
Publication: US 2015/0349077
Iii-V Layers for N-Type and P-Type Mos Source-Drain Contacts
Patent: 9,397,102 →
Application: 14/875,167 →
Publication: US 2016/0027781
Group Iii-N Nanowire Transistors
Patent: 9,397,188 →
Application: 14/936,609 →
Publication: US 2016/0064512
Self-Aligned Contact Metallization for Reduced Contact Resistance
Patent: 9,754,940 →
Application: 14/981,206 →
Publication: US 2016/0118384
Common-Substrate Semiconductor Devices Having Nanowires or Semiconductor Bodies with Differing Material Orientation or Composition
Patent: 9,691,843 →
Application: 14/996,038 →
Publication: US 2016/0133735
Redistribution Layer Lines
Patent: 9,741,651 →
Application: 15/052,505 →
Publication: US 2017/0243815
Deep Gate-All-Around Semiconductor Device Having Germanium or Group Iii-V Active Layer
Patent: 9,640,671 →
Application: 15/134,093 →
Publication: US 2016/0233344
Integrated Circuit Package Stack
Patent: 9,859,253 →
Application: 15/196,937 →
Publication: US 2018/0005989
Group Iii-N Nanowire Transistors
Patent: 9,691,857 →
Application: 15/197,615 →
Publication: US 2016/0315153
Iii-V Layers for N-Type and P-Type Mos Source-Drain Contacts
Patent: 9,705,000 →
Application: 15/212,991 →
Publication: US 2016/0329431
Nanowire Structures Having Non-Discrete Source and Drain Regions
Application: 15/405,899 →
Publication: US 2017/0141239
CMOS HAVING A Ge CHANNEL PMOS AND III-V CHANNEL NMOS FORMED ON A SILICON SUBSTRATE
Application: 15/435,245 →
Publication: US 2017/0162453
Deep Gate-All-Around Semiconductor Device Having Germanium or Group Iii-V Active Layer
Application: 15/465,448 →
Publication: US 2017/0194506
Group Iii-N Nanowire Transistors
Application: 15/623,165 →
Publication: US 2017/0288022
Redistribution Layer Lines
Application: 15/677,835 →
Publication: US 2018/0068939
Deep Gate-All-Around Semiconductor Device Having Germanium or Group Iii-V Active Layer
Application: 16/011,308 →
Publication: US 2018/0301563
Group Iii-N Nanowire Transistors
Application: 16/246,356 →
Publication: US 2019/0165106
Nanowire Structures Having Wrap-Around Contacts
Application: 16/592,380 →
Publication: US 2020/0035818
Nanowire Structures Having Non-Discrete Source and Drain Regions
Application: 16/740,089 →
Publication: US 2020/0152797
Nanowire Structures Having Wrap-Around Contacts
Application: 17/072,992 →
Publication: US 2021/0036137
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest May 27, 2005
From: MOYER, WILLIAM C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 016629/0928 →
Assignment of Assignor's Interest May 27, 2005
From: MOYER, WILLIAM C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 016631/0004 →
Assignment of Assignor's Interest Jun 21, 2005
From: KAVALIEROS, JACK; CAPPELLANI, ANNALISA; BRASK, JUSTIN K.; DOCZY, MARK L.
To: INTEL CORPORATION
Reel/Frame 016716/0202 →
Assignment of Assignor's Interest Dec 27, 2005
From: KAVALIEROS, JACK T.; BRASK, JUSTIN K.; DATTA, SUMAN; DOYLE, BRIAN S.
To: INTEL CORPORATION
Reel/Frame 017425/0863 →
Security Agreement Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
Security Agreement Jul 11, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021217/0368 →
Assignment of Assignor's Interest Jan 14, 2009
From: FINKELSTEIN, LEV; ROTEM, EFRAIM; COHEN, AVIAD; RONEN, RONNY
To: INTEL CORPORATION
Reel/Frame 022104/0707 →
Assignment of Assignor's Interest Apr 27, 2009
From: JIN, BEEN-YIH; KAVALIEROS, JACK T.; METZ, MATTHEW V.; RADOSAVLIEVIC, MARKO
To: INTEL CORPORATION
Reel/Frame 022600/0156 →
Assignment of Assignor's Interest Jan 11, 2010
From: RANADE, PUSHKAR; ZAWADZKI, KEITH; AUTH, CHRISTOPHER
To: INTEL CORPORATION
Reel/Frame 023760/0126 →
Assignment of Assignor's Interest Mar 29, 2010
From: SELL, BERNHARD; GHANI, TAHIR; MURTHY, ANAND; GOMEZ, HARRY
To: INTEL CORPORATION
Reel/Frame 024174/0549 →
Security Agreement May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
Assignment of Assignor's Interest Jul 8, 2010
From: JIN, BEEN-YIH; DOYLE, BRIAN S.; KAVALIEROS, JACK T.; CHAU, ROBERT S.
To: INTEL CORPORATION
Reel/Frame 024654/0123 →
Assignment of Assignor's Interest Oct 12, 2010
From: NARAYAN, SRIRAM; SHUMARAYEV, SERGEY
To: ALTERA CORPORATION
Reel/Frame 025123/0897 →
Assignment of Assignor's Interest Jul 28, 2011
From: SHAH, UDAY; CHU-KUNG, BENJAMIN; JIN, BEEN-YIH; PILLARISETTY, RAVI
To: INTEL CORPORATION
Reel/Frame 026666/0335 →
Assignment of Assignor's Interest Jan 10, 2012
From: MEYER, THORSTEN; OFNER, GERALD; WAIDHAS, BERND
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027508/0672 →
Security Agreement Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
Security Agreement Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
Release of Security Interest Jan 23, 2015
From: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034799/0554 →
Release of Security Interest Jan 23, 2015
From: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034799/0388 →
Assignment of Assignor's Interest Jan 23, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: INTEL CORPORATION
Reel/Frame 034802/0847 →
Release of Security Interest Jan 23, 2015
From: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034799/0777 →
Release of Security Interest Jan 23, 2015
From: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034799/0664 →
Assignment of Assignor's Interest Jun 22, 2015
From: SPRANGLE, ERIC; ROHILLAH, ANWAR; CAVIN, ROBERT
To: INTEL CORPORATION
Reel/Frame 035878/0162 →
Assignment of Assignor's Interest Jun 22, 2015
From: SPRANGLE, ERIC; ROHILLAH, ANWAR; CAVIN, ROBERT
To: INTEL CORPORATION
Reel/Frame 035878/0151 →
Change of Name Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →