Self-aligned contact metallization for reduced contact resistance
View Patent ↗Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures.
1. An integrated circuit, comprising:
a substrate having a number of channel regions;
p-type source/drain regions in the substrate and adjacent to a corresponding channel region;
n-type source/drain regions in the substrate and adjacent to a corresponding channel region;
a p-type germanium layer over at least a portion of the p-type source/drain regions; and
an n-type III-V semiconductor material layer over at least a portion of the n-type source drain regions.
2. The integrated circuit of claim 1 , further comprising:
contact resistance reducing metal over the p-type germanium layer and the n-type III-V semiconductor material layer; and
source/drain metal contact plugs on the contact resistance reducing metal.
3. The integrated circuit of claim 2 , further comprising:
a gate electrode above each channel region, wherein a gate dielectric layer is provided between each gate electrode and a corresponding channel region.
4. The integrated circuit of claim 1 , further comprising:
an insulation layer over the substrate, the insulation layer having a contact trench formed over each of the p-type source/drain regions and the n-type source/drain regions, wherein the n-type III-V semiconductor material layer is entirely within the contact trenches formed over the n-type source/drain regions.
5. The integrated circuit of claim 4 , wherein the p-type germanium layer is entirely within the contact trenches formed over the p-type source/drain regions.
6. The integrated circuit of claim 4 , wherein the n-type III-V semiconductor material layer comprises at least one of aluminum, gallium, indium, phosphorus, arsenide, and antimonide.
7. The integrated circuit of claim 6 , wherein the insulation layer comprises at least one of silicon dioxide and silicon nitride.
8. The integrated circuit of claim 7 , wherein the substrate is a bulk silicon substrate.
9. The integrated circuit of claim 8 , wherein the p-type source/drain regions and n-type source/drain regions are silicon or germanium or a silicon germanium alloy.
10. The integrated circuit of claim 1 , wherein the p-type source/drain regions and n-type source/drain regions have a planar diffusion region.
11. The integrated circuit of claim 1 , wherein the p-type source/drain regions and n-type source/drain regions have a fin shaped diffusion region.
12. The integrated circuit of claim 1 , wherein the p-type source/drain regions and n-type source/drain regions have a wire shaped diffusion region.
13. The integrated circuit of claim 1 , wherein the p-type source/drain regions and n-type source/drain regions are raised relative to their corresponding channel region.
14. An integrated circuit, comprising:
a substrate having a number of fins extending therefrom, each fin having a channel region;
p-type source/drain regions in or on the substrate and adjacent to a corresponding channel region;
n-type source/drain regions in or on the substrate and adjacent to a corresponding channel region;
a p-type germanium layer over at least a portion of the p-type source/drain regions; and
an n-type III-V semiconductor material layer over at least a portion of the n-type source drain regions.
15. The integrated circuit of claim 14 , further comprising:
an insulation layer over the substrate, the insulation layer having a contact trench formed over each of the p-type source/drain regions and the n-type source/drain regions, wherein the n-type III-V semiconductor material layer is entirely within the contact trenches formed over the n-type source/drain regions;
a gate electrode adjacent each channel region, wherein a gate dielectric layer is provided between each gate electrode and a corresponding channel region;
contact resistance reducing metal over the p-type germanium layer and the n-type III-V semiconductor material layer; and
source/drain metal contact plugs on the contact resistance reducing metal.
16. The integrated circuit of claim 14 , wherein each of the p-type source/drain regions and n-type source/drain regions have one of a wire shaped or a fin shaped diffusion area.
17. An integrated circuit, comprising:
a substrate having a number of fins extending therefrom, each fin associated with a nanowire channel region;
p-type source/drain regions in or on the substrate and adjacent to a corresponding channel region;
n-type source/drain regions in or on the substrate and adjacent to a corresponding channel region;
a p-type germanium layer over at least a portion of the p-type source/drain regions; and
an n-type III-V semiconductor material layer over at least a portion of the n-type source drain regions.
18. The integrated circuit of claim 17 , further comprising:
an insulation layer over the substrate, the insulation layer having a contact trench formed over each of the p-type source/drain regions and the n-type source/drain regions, wherein the n-type III-V semiconductor material layer is entirely within the contact trenches formed over the n-type source/drain regions;
a gate electrode adjacent each channel region, wherein a gate dielectric layer is provided between each gate electrode and a corresponding channel region;
contact resistance reducing metal over the p-type germanium layer and the n-type III-V semiconductor material layer; and
source/drain metal contact plugs on the contact resistance reducing metal.
19. The integrated circuit of claim 17 , wherein each of the p-type source/drain regions and n-type source/drain regions have one of a wire shaped or a fin shaped diffusion area.
20. The integrated circuit of claim 19 , wherein at least one of the p-type source/drain regions and/or n-type source/drain regions has a wire shaped diffusion area including multiple wires.