Nanowire structures having wrap-around contacts

1. A nanowire semiconductor device, comprising:

a nanowire disposed above a substrate;

a channel region disposed in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region is a smallest perimeter of the nanowire;

a gate electrode stack surrounding the entire perimeter of the channel region;

a pair of source and drain regions disposed in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the source and drain regions are approximately the same, and are greater than the perimeter of the channel region at locations immediately adjacent the channel region, and wherein the smallest perimeter of the nanowire is at the locations where the source and drain regions are immediately adjacent the channel region;

a pair of conductive contacts, a first of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the source region, and a second of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the drain region, wherein the pair of conductive contacts has an uppermost surface co-planar with an uppermost surface of the gate electrode stack;

a pair of spacers disposed between the gate electrode stack and the pair of conductive contacts; and

an intervening semiconductor material below and in contact with the nanowire but not along sidewalls of the nanowire at a location beneath the pair of spacers.

2. The nanowire semiconductor device of claim 1 , wherein the channel region has a width and a height, the width approximately the same as the height, and wherein each of the source and drain regions has a width and a height, the width approximately the same as the height.

3. The nanowire semiconductor device of claim 1 , wherein the nanowire consists essentially of silicon, and the entire perimeter of each of the source and drain regions is an exposed <111> silicon surface.

4. The nanowire semiconductor device of claim 1 , further comprising:

a doping layer disposed on and completely surrounding the perimeter of each of the source and drain regions, between the source and drain regions and the pair of conductive contacts.

5. The nanowire semiconductor device of claim 1 , wherein the gate electrode stack comprises a metal gate and a high-K gate dielectric, and the nanowire comprises silicon, germanium, or a combination thereof.

6. The nanowire semiconductor device of claim 1 , wherein the channel region has a width and a height, the width substantially greater than the height, and wherein each of the source and drain regions has a width and a height, the width substantially greater than the height.

7. The nanowire semiconductor device of claim 6 , wherein the nanowire consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <110> silicon surfaces, and the perimeter along the height of each of the source and drain regions comprises exposed <100> silicon surfaces.

8. The nanowire semiconductor device of claim 1 , wherein the channel region has a width and a height, the width substantially less than the height, and wherein each of the source and drain regions has a width and a height, the width substantially less than the height.

9. The nanowire semiconductor device of claim 8 , wherein the nanowire consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <100> silicon surfaces, and the perimeter along the height of each of the source and drain regions comprises exposed <110> silicon surfaces.

10. A semiconductor device, comprising:

a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising:

a discrete channel region disposed in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region is a smallest perimeter of the nanowire;

a pair of discrete source and drain regions disposed in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the source and drain regions are approximately the same, and are greater than the perimeter of the channel region at locations immediately adjacent the channel region, and wherein the smallest perimeter of the nanowire is at the locations where the source and drain regions are immediately adjacent the channel region;

a gate electrode stack surrounding and in contact with the entire perimeter of each of the channel regions;

a pair of conductive contacts, a first of the pair of conductive contacts completely surrounding the perimeter of each of the source regions, and a second of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of each of the drain regions, wherein the pair of conductive contacts has an uppermost surface co-planar with an uppermost surface of the gate electrode stack;

a pair of spacers disposed between the gate electrode stack and the pair of conductive contacts; and

an intervening semiconductor material between and in contact with the plurality of vertically stacked nanowires but not along sidewalls of the nanowires at a location beneath the pair of spacers.

11. The semiconductor device of claim 10 , wherein each of the channel regions has a width and a height, the width approximately the same as the height, and wherein each of the source and drain regions has a width and a height, the width approximately the same as the height.

12. The semiconductor device of claim 10 , wherein each of the nanowires consists essentially of silicon, and the entire perimeter of each of the source and drain regions is an exposed <111> silicon surface.

13. The semiconductor device of claim 10 , further comprising:

a doping layer disposed on and completely surrounding the perimeter of each of the source and drain regions, between the source and drain regions and the pair of conductive contacts.

14. The semiconductor device of claim 10 , wherein the gate electrode stack comprises a metal gate and a high-K gate dielectric, and each of the nanowires comprises silicon, germanium, or a combination thereof.

15. The semiconductor device of claim 10 , wherein each of the channel regions has a width and a height, the width substantially greater than the height, and wherein each of the source and drain regions has a width and a height, the width substantially greater than the height.

16. The semiconductor device of claim 15 , wherein each of the nanowires consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <110> silicon surfaces, and the perimeter along the height of each of the source and drain regions comprises exposed <100> silicon surfaces.

17. The semiconductor device of claim 10 , wherein each of the channel regions has a width and a height, the width substantially less than the height, and wherein each of the source and drain regions has a width and a height, the width substantially less than the height.

18. The semiconductor device of claim 17 , wherein each of the nanowires consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <100> silicon surfaces, and the perimeter along the height of each of the source and drain regions comprises exposed <110> silicon surfaces.

19. A method of fabricating a nanowire semiconductor device, the method comprising:

forming a nanowire above a substrate;

forming a channel region in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region is a smallest perimeter of the nanowire;

forming a gate electrode stack surrounding the entire perimeter of the channel region;

forming a pair of source and drain regions in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the source and drain regions are approximately the same, and are greater than the perimeter of the channel region at locations immediately adjacent the channel region, and wherein the smallest perimeter of the nanowire is at the locations where the source and drain regions are immediately adjacent the channel region;

forming a pair of conductive contacts, a first of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the source region, and a second of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the drain region, wherein the pair of conductive contacts has an uppermost surface co-planar with an uppermost surface of the gate electrode stack

forming a pair of spacers disposed between the gate electrode stack and the pair of conductive contacts, wherein an intervening semiconductor material is below and in contact with the nanowire but not along sidewalls of the nanowire at a location beneath the pair of spacers.

20. The method of claim 19 , wherein forming the channel region comprises removing a portion of the nanowire.

21. The method of claim 19 , wherein forming the pair of source and drain regions comprises forming a doping layer on and completely surrounding the perimeter of each of the source and drain regions.

22. The method of claim 19 , wherein forming the pair of source and drain regions comprises growing a portion of the nanowire.

23. The method of claim 22 , wherein the nanowire consists essentially of silicon, and growing the portion of the nanowire comprises forming exposed <111> silicon surfaces along the entire perimeter of each of the source and drain regions.

24. The method of claim 23 , wherein forming the exposed <111> silicon surfaces comprises using a deposition and selective etch process.