Integrated circuit package stack
Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package.
1. An integrated circuit (IC) package stack, comprising:
a first IC package, a first side of the first IC package to be mounted to a circuit board, the first IC package includes:
a first die;
a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side;
a first set of vias that communicatively couples the contacts on the first side of the first IC package to the first redistribution layer; and
a second set of vias that communicatively couples the first redistribution layer to the contacts on the second side of the first IC package, wherein the first set of vias are formed within a substrate of the first IC package and the second set of vias are formed within a molded layer of the first IC package; and
a second IC package mounted to the second side of the first IC package, the second IC package includes:
a second die;
a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package.
2. The IC package stack of claim 1 , further comprising a ball grid array (BGA) located between the second side of the first IC package and the side of the second IC package, wherein the BGA communicatively couples the contacts on the second side of the first IC package to the contacts of the second IC package.
3. The IC package stack of claim 1 , further comprising under-fill material located between the second side of the first IC package and the side of the second IC package.
4. The IC package stack of claim 1 , wherein a layout of the first redistribution layer is different than a layout of the second redistribution layer.
5. The IC package stack of claim 1 , wherein the first set of vias extend from the contacts on the first side of the first IC package to the first redistribution layer, and wherein the first set of vias are formed around the first die.
6. The IC package stack of claim 1 , wherein the second IC package further includes: a set of vias that communicatively couple the contacts of the second IC package to the second redistribution layer.
7. The IC package stack of claim 6 , wherein the second IC package further includes a second set of vias that communicatively couple the second redistribution layer to contacts on a second side of the second IC package, the second side of the second IC package opposite to the first side of the second IC package, and wherein the IC package stack further includes:
a third IC package, the third IC package mounted to the second side of the second IC package, the third IC package includes:
a third die; and
a third redistribution layer that communicatively couples contacts on a side of the third IC package to the third die, the contacts of the third IC package communicatively coupled to the contacts on the second side of the second IC package.
8. The IC package stack of claim 7 , wherein a layout of the third redistribution layer is different than a layout of the second redistribution layer, and wherein the layout of the third redistribution layer is different than a layout of the first redistribution layer.
9. The IC package stack of claim 1 , wherein the first die is located between the first redistribution layer and the second side of the first IC package.
10. A system, comprising:
a circuit board; and
an integrated circuit (IC) package stack communicatively coupled to the circuit board, the IC package stack including:
a first IC package, a first side of the first IC package coupled to the circuit board, the first IC package includes:
a first die;
a first redistribution layer that communicatively couples one or more contacts on the first side of the first IC package to one or more contacts on a second side of the first IC package, the second side of the first IC package opposite to the first side of the first IC package;
a first set of vias that communicatively couples the one or more contacts on the first side of the first IC package to the first redistribution layer; and
a second set of vias that communicatively couples the first redistribution layer to the one or more contacts on the second side of the first IC package, wherein the first set of vias are formed within a substrate of the first IC package and the second set of vias are formed within a molded layer of the first IC Package; and
a second IC package mounted to the second side of the first IC package, the second IC package including:
a second die; and
a second redistribution layer that communicatively couples, via one or more vias, one or more contacts on a side of the second IC package to the second die, the one or more contacts on the side of the second IC package communicatively coupled to the one or more contacts on the second side of the first IC package.
11. The system of claim 10 , further comprising a ball grid array (BGA) located between the second side of the first IC package and the side of the second IC package, wherein the BGA communicatively couples the second set of vias of the first IC package to the one or more vias of the second IC package.
12. The system of claim 10 , wherein the one or more vias of the second IC package are formed in a substrate and a molded layer of the second IC package.
13. The system of claim 10 , wherein the first redistribution layer further communicatively couples the one or more contacts on the first side of the first IC package to the first die.
14. The system of claim 10 , wherein the second redistribution layer further communicatively couples, via the one or more vias, the one or more contacts on the side of the second IC package to one or more contacts on a second side of the second IC package, the second side of the IC package opposite to the side of the second IC package, and wherein the IC package stack further includes:
a third IC package mounted to the second side of the second IC package, the third IC package includes:
a third die; and
a third redistribution layer that communicatively couples, via one or more vias, one or more contacts on a side of the third IC package to the third die, wherein the one or more contacts on the side of the third IC package are communicatively coupled to the one or more contacts on the second side of the second IC package.