Method for handling very thin device wafers
View Patent ↗A structure and method of handling a device wafer during through-silicon via (TSV) processing are described in which a device wafer is bonded to a temporary support substrate with a permanent thermosetting material. Upon removal of the temporary support substrate a planar frontside bonding surface including a reflowed solder bump and the permanent thermosetting material is exposed.
1. A method comprising:
providing a device wafer including a front surface and a solder bump formed over the front surface;
providing a support substrate including a planar wetting surface, wherein a layer of thermosetting material is formed on the planar wetting surface;
bonding the device wafer to the support substrate under heat and pressure, wherein the bonding comprises:
penetrating the layer of thermosetting material with the solder bump;
wetting the planar wetting surface with the solder bump while reflowing the solder bump; and
at least partially curing the thermosetting material; and
removing the support substrate to expose a planar frontside bonding surface including the reflowed solder bump and the at least partially cured thermosetting material.
2. The method of claim 1 , further comprising forming a via extending between the front surface and a back surface of the device wafer after bonding the device wafer to the support substrate.
3. The method of claim 2 , comprising forming the via prior to removing the support substrate.
4. The method of claim 2 , comprising grinding or polishing a back surface of the device wafer to reduce the thickness of the device wafer after bonding the device wafer to the support substrate and prior to forming the via.
5. The method of claim 2 , wherein the planar wetting surface comprises a material selected from the group consisting of nickel, gold, platinum, palladium, cobalt, copper, iron and steel.
6. The method of claim 2 , wherein the support substrate comprises a bulk substrate and a coating layer comprising the planar wetting surface.
7. The method of claim 1 , further comprising forming a via extending between the front surface and a back surface of the device wafer prior to bonding the device wafer to the support substrate.
8. The method of claim 1 , wherein the planar wetting surface comprises a material selected from the group consisting of nickel, gold, platinum, palladium, cobalt, copper, iron and steel.
9. The method of claim 8 , wherein the support substrate is a bulk substrate.
10. The method of claim 9 , wherein the bulk substrate is copper.
11. The method of claim 8 , wherein the support substrate comprises a bulk substrate and a coating layer which comprises the planar wetting surface.
12. The method of claim 1 , further comprising spin coating or laminating the layer of thermosetting material on the planar wetting surface of the support substrate.
13. The method of claim 12 , wherein the layer of thermosetting material is b-stage cured prior to bonding the device wafer to the support substrate.
14. The method of claim 1 further comprising:
attaching a first die to the planar frontside bonding surface; and
attaching a second die to a back surface of the device wafer.