Structure having a planar bonding surface
View Patent ↗A structure and method of handling a device wafer during through-silicon via (TSV) processing are described in which a device wafer is bonded to a temporary support substrate with a permanent thermosetting material. Upon removal of the temporary support substrate a planar frontside bonding surface including a reflowed solder bump and the permanent thermosetting material is exposed.
1. A structure comprising:
a semiconductor substrate having a front surface, a back surface, and a via extending through the semiconductor substrate between the back surface and the front surface;
a reflowed solder bump formed over the front surface; and
a cured thermosetting material formed over the front surface and around the reflowed solder bump, wherein the cured thermosetting material and reflowed solder bump form an exposed planar frontside bonding surface.
2. The structure of claim 1 , wherein the via comprises copper.
3. The structure of claim 1 , wherein the cured thermosetting material is selected from the group consisting of a cured epoxy resin, cured phenolic resin, cured polyimide, and cured poly-benzoxasole (PBO).
4. A 3D packaging structure comprising:
a substrate;
a chip comprising:
a semiconductor substrate having a front surface, a back surface, and a via extending through the semiconductor substrate between the back surface and the front surface;
a reflowed solder bump formed over the front surface; and
a cured thermosetting material formed over the front surface and around the reflowed solder bump, wherein the cured thermosetting material and reflowed solder bump form an exposed planar frontside bonding surface;
wherein the planar frontside bonding surface is attached to the substrate.
5. The 3D packaging structure of claim 4 , further comprising a second chip stacked over the chip.
6. The 3D packaging structure of claim 5 , further comprising a system comprising a bus communicatively coupled to the 3D packaging structure.