Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby
View Patent ↗Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a ( 100 ) plane to form at least one ( 111 ) region in the recessed source/drain region.
1. A method comprising:
dry etching a portion of a source/drain region of a transistor; and
selectively wet etching the source drain region along the ( 100 ) plane to form at least one ( 111 ) region in the recessed source/drain region; and
growing an epitaxial material along the at least one ( 111 ) region, wherein a portion of the epitaxial material is raised above a gate region plane, and wherein the epitaxial material fills the source/drain region.
2. The method of claim 1 further comprising wherein a depth of an isolation edge is set by the dry etch.
3. The method of claim 1 further comprising:
wherein a ( 111 ) region is formed along an isolated edge; and growing an epitaxial material on the ( 111 ) region formed along the isolation edge.
4. The method of claim 1 further comprising wherein the at least one ( 111 ) region form a vertex underneath a gate region.
5. The method of claim 1 further comprising wherein a depth of a recessed edge is set by the wet etch.
6. The method of claim 5 wherein optimizing the depth of at least one of the dry etch and the wet etch improves the electrical performance of the transistor.
7. The method of claim 6 further comprising forming a contact to the filled source/drain region, wherein the contact is fully landed on the source/drain region.
8. A structure comprising:
a source/drain region of a transistor comprising at least one ( 111 ) region, wherein the at least one ( 111 ) region forms a vertex underneath a gate region of the transistor; and
an epitaxial material disposed within the source/drain region, wherein a raised portion of the epitaxial material is disposed above the gate region.
9. The structure of claim 8 wherein the epitaxial material comprises silicon germanium.
10. The structure of claim 8 wherein the epitaxial material is disposed on a ( 111 ) plane along an isolation edge region.
11. The structure of claim 8 wherein the raised portion is raised at least about 10 nm above the gate region.
12. The structure of claim 8 further comprising a contact disposed on the source/drain region, wherein the contact is fully landed on the source drain region.