Self-aligned contact metallization for reduced contact resistance
View Patent ↗Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures.
1. An integrated circuit, comprising:
a p-type germanium layer directly on at least a portion of a p-type source region and a p-type drain region; and
an n-type III-V semiconductor material layer directly on at least a portion of an n-type source region and an n-type drain region.
2. The integrated circuit of claim 1 , comprising:
a substrate having a number of channel regions;
wherein the p-type source region and the p-type drain region are at least one of in and on the substrate and adjacent to a corresponding channel region; and
wherein the n-type source region and the n-type drain region are at least one of in and on the substrate and adjacent to a corresponding channel region.
3. The integrated circuit of claim 2 , further comprising:
a gate electrode above each channel region, wherein a gate dielectric is provided between each gate electrode and a corresponding channel region.
4. The integrated circuit of claim 2 , further comprising:
insulation material over the substrate, the insulation material having a contact trench formed over each of the p-type source region, the p-type drain region, the n-type source region, and the n-type drain region, wherein the n-type III-V semiconductor material layer is entirely within the contact trenches formed over the n-type source region and the n-type drain region.
5. The integrated circuit of claim 4 , wherein the p-type germanium layer is entirely within the contact trenches formed over the p-type source region and the p-type drain region.
6. The integrated circuit of claim 2 , wherein the substrate is a bulk silicon substrate.
7. The integrated circuit of claim 6 , wherein the p-type source region and the p-type drain region are silicon or germanium or a silicon germanium alloy.
8. The integrated circuit of claim 6 , wherein the n-type source region and the n-type drain region are silicon or germanium or a silicon germanium alloy.
9. The integrated circuit of claim 1 , wherein the n-type III-V semiconductor material layer comprises at least one of aluminum, gallium, indium, phosphorus, arsenic, and antimony.
10. The integrated circuit of claim 1 , wherein the p-type source region, the p-type drain regions, the n-type source region and the n-type drain region have a planar diffusion region.
11. The integrated circuit of claim 1 , wherein the p-type source region, the p-type drain region, the n-type source region, and the n-type drain region have a fin shaped diffusion region.
12. The integrated circuit of claim 1 , wherein the p-type source region, the p-type drain region, the n-type source region, and the n-type drain region have a wire shaped diffusion region.
13. The integrated circuit of claim 1 , wherein each of the p-type source region, the p-type drain region, the n-type source region and the n-type drain region are associated with a channel region, and at least some of the p-type source region, the p-type drain region, the n-type source region, and the n-type drain region are raised relative to their corresponding channel region.
14. The integrated circuit of claim 1 , further comprising:
contact resistance reducing metal over the p-type germanium layer and the n-type III-V semiconductor material layer; and
source metal contact and drain metal contact plugs on the contact resistance reducing metal.
15. An integrated circuit, comprising:
a substrate having a number of fins extending therefrom, each fin having a channel region;
a p-type source region and a p-type drain region at least one of in and on the substrate and adjacent to a corresponding channel region;
an n-type source region and an n-type drain region at least one of in and on the substrate and adjacent to a corresponding channel region;
a p-type germanium layer directly on at least a portion of the p-type source region and the p-type drain region; and
an n-type III-V semiconductor material layer directly on at least a portion of the n-type source region and the n-type drain region.
16. The integrated circuit of claim 15 , further comprising:
insulation material over the substrate, the insulation material having a contact trench formed over each of the p-type source region, the p-type drain region, the n-type source region, and the n-type drain region, wherein the n-type III-V semiconductor material layer is entirely within the contact trenches formed over the n-type source region and the n-type drain region;
a gate electrode adjacent each channel region, wherein a gate dielectric is provided between each gate electrode and a corresponding channel region;
contact resistance reducing metal over the p-type germanium layer and the n-type III-V semiconductor material layer; and
source metal contact plugs and drain metal contact plugs on the corresponding contact resistance reducing metal.
17. The integrated circuit of claim 15 , wherein at least one of the p-type source region, the p-type drain region, the n-type source region, and the n-type drain region has one or more wires.
18. An integrated circuit, comprising:
a substrate having a number of fins extending therefrom, each fin having a channel region, at least one of the channel regions configured with one or more nanowires;
a p-type source region and a p-type drain region at least one of in and on the substrate and adjacent to a corresponding channel region;
an n-type source region and an n-type drain region in and on the substrate and adjacent to a corresponding channel region;
a p-type germanium layer directly on at least a portion of the p-type source region and the p-type drain region; and
an n-type III-V semiconductor material layer directly on at least a portion of the n-type source drain regions.
19. The integrated circuit of claim 18 , further comprising:
an insulation material over the substrate, the insulation material having a contact trench formed over each of the p-type source region, the p-type drain region, the n-type source region, and the n-type drain region, wherein the n-type III-V semiconductor material layer is entirely within the contact trenches formed over the n-type source region and the n-type drain region;
a gate electrode adjacent each channel region, wherein a gate dielectric is provided between each gate electrode and a corresponding channel region;
contact resistance reducing metal over the p-type germanium layer and the n-type III-V semiconductor material layer; and
a source metal contact plug and a drain metal contact plug on the contact resistance reducing metal.
20. The integrated circuit of claim 18 , wherein at least one of the p-type source region and the p-type drain region, the n-type source region, and the n-type drain region has one or more wires.