Memory management circuitry translation information retrieval during debugging
View Patent ↗A system for obtaining translation information from a data processing system. The system includes circuitry for receiving an external request for translation information. The circuitry determines whether the requested translation information is present in memory management circuitry of a data processing system. If the translation information is not present in the memory management circuitry, the circuitry requests retrieval of the information by a processor core. In one embodiment, the request is performed by generating an interrupt to the processor core. In other embodiments, the request is preformed by requesting the activation of a program thread to be executed by the processor core.
1. A method for obtaining translation information from a data processor, the data processor including a processor core and memory management circuitry, the method comprising:
requesting, by circuitry external to the data processor, translation information from the memory management circuitry, wherein the translation information is utilized in performing processor operations of the data processor, wherein the requesting is performed transparent to the operation of the processor core, wherein the requesting includes debug circuitry providing a request for the translation information to the memory management circuitry;
determining whether the requested translation information is present within memory management circuitry wherein the determining is performed transparent to the operation of the processor core;
if the requested translation information is determined not to be present within the memory management circuitry, requesting retrieval of the requested translation information by the processor core.
2. The method of claim 1 wherein the requesting retrieval includes generating an interrupt to the processor core.
3. The method of claim 2 wherein the processor core handles interrupts of different priority levels, wherein the generating an interrupt includes generating an interrupt of a lower priority level.
4. The method of claim 1 wherein the requesting retrieval includes requesting an activation of a program thread to be executed by the processor core.
5. The method of claim 4 wherein the processor core executes program threads of different priority levels, wherein the activation of the program thread includes the activation of the program thread of a lower priority level.
6. The method of claim 4 wherein a priority level of the program thread is programmable.
7. The method of claim 1 wherein the requesting retrieval includes indicating a priority level of the retrieval by the processor core.
8. The method of claim 1 further comprising:
the processor core retrieving the requested translation information;
providing the requested translation information external to the data processor.
9. The method of claim 8 wherein the data processor is implemented on an integrated circuit, the method further comprising:
providing the requested translation information external to the integrated circuit.
10. The method of claim 9 wherein the requesting translation information from the memory management circuitry is generated external to the integrated circuit.
11. The method of claim 9 wherein the integrated circuit includes at least one external debug terminal, wherein the requested translation information is provided external to the data processor via the at least one external debug terminal.
12. The method of claim 1 wherein the requesting retrieval by the processor core is performed by debug circuitry located within the data processor.
13. The method of claim 1 wherein the requesting retrieval of the requested translation information by the processor core is performed by circuitry of the memory management circuitry.
14. The method of claim 1 wherein:
the requesting translation information includes a request for translation information associated with a virtual address.
15. The method of claim 14 wherein the request includes a request for a physical address information associated with the virtual address.
16. A data processing system comprising:
a data processor, the data processor including:
a processor core;
memory management circuitry operably coupled to the processor core, the memory management circuitry storing translation information, wherein the translation information is utilized in performing processor operations of the data processor;
debug circuitry, wherein the debug circuitry is operably coupled to receive external requests for translation information, wherein the external requests are received external to the data processor, the debug circuitry configured to obtain requested translation information from the memory management circuitry transparent to the operation of the processor core wherein the debug circuitry is configured to request the requested translation information from the memory management circuitry transparent to the operation of the processor core, and the debug circuitry is coupled to provide obtained translation information external to the data processor, the debug circuitry is operably coupled to the processor core to request the retrieval of translation information by the processor core.
17. The data processing system of claim 16 wherein the debug circuitry requests retrieval of translation information by the processor core in response to a determination that the translation information is not present in the memory management circuitry.
18. The data processing system of claim 16 wherein the debug circuitry requests retrieval of translation information by the processor core by generating an interrupt to the processor core.
19. The data processing system of claim 16 wherein the debug circuitry requests retrieval of translation information by the processor core by requesting an activation of a processing thread by the processor core.
20. The data processing system of claim 16 wherein data processor, memory management circuitry, and the debug circuitry are implemented on an integrated circuit, wherein the integrated circuit includes at least one external debug terminal, the debug circuitry operably coupled to the at least one external debug terminal to receive requests for translation information and to provide retrieved translation information including translation information retrieved by the processor core.
21. A method of debugging a data processor, the data processor including a processor core and memory management circuitry, the processor core and memory management circuitry are implemented in an integrated circuit, the method comprising:
requesting, by circuitry external to the integrated circuit, translation information from the memory management circuitry, wherein the requesting is performed transparent to the operation of the processor core, wherein the requesting includes debug circuitry providing a request for the translation information to the memory management circuitry;
determining whether the requested translation information is present within the memory management circuitry, wherein the determining is performed without utilizing a processor core operation;
if the requested translation information is determined not to be present within the memory management circuitry, requesting retrieval of the requested translation information by the processor core;
retrieving the requested translated information by the processor core in response to the requesting retrieval;
providing the requested translation information retrieved by the processor core to the circuitry external to the integrated circuit via at least one external debugging terminal of the integrated circuit;
using the translation information retrieved by the processor core to debug code being executed by the processor core.