Deep gate-all-around semiconductor device having germanium or group III-V active layer
View Patent ↗Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
1. A non-planar semiconductor device, comprising:
a buffer layer disposed on a substrate;
an active layer disposed on the buffer layer;
a gate electrode stack disposed on and completely surrounding a channel region of the active layer, and is disposed in a trench in the buffer layer;
source and drain regions disposed in the active layer and in the buffer layer, on either side of the gate electrode stack, wherein the gate electrode stack is disposed to a depth in the buffer layer sufficiently below a depth of the source and drain regions in the buffer layer to block a substantial portion of leakage from the source region to the drain region; and
isolation regions adjacent the source and drain regions and disposed at least partially into the buffer layer, wherein the gate electrode stack is disposed to a depth in the buffer layer deeper than a depth of the isolation regions.
2. The non-planar semiconductor device of claim 1 , wherein the channel region of the active layer has a lower band gap than any portion of the buffer layer.
3. The non-planar semiconductor device of claim 2 , wherein the channel region of the active layer consists essentially of germanium, and the buffer layer comprises silicon germanium.
4. The non-planar semiconductor device of claim 2 , wherein the active layer and the buffer layer each comprise a group III-V material.
5. The non-planar semiconductor device of claim 1 , wherein the gate electrode stack is disposed to a depth in the buffer layer approximately 2-4 times the depth of the source and drain regions in the buffer layer.
6. The non-planar semiconductor device of claim 1 , wherein the gate electrode stack comprises a high-k gate dielectric layer lining the trench, and a metal gate electrode within the high-k gate dielectric layer.
7. The non-planar semiconductor device of claim 1 , further comprising:
one or more nanowires disposed in a vertical arrangement above the active layer, wherein the gate electrode stack is disposed on and completely surrounds a channel region of each of the nanowires.