Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications
View Patent ↗A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1−xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1−yGey and a covering region comprising SiO2 and enclosing the center region.
1. A method to form a microelectronic structure, comprising:
providing a substrate including a lower Si substrate and an insulating layer on the substrate;
forming a projection on the substrate projecting above the insulating layer comprising a plurality of interleaved Si1−xGex and Si layers; and
oxidizing the projection to form a plurality of nanowires and an insulation covering, wherein the insulation covering is a single structure surrounding each of the plurality of nanowires.
2. The method of claim 1 , wherein oxidizing the projection comprises oxidizing the projection to form a plurality of nanowires surrounded by a SiO2 insulation covering.
3. The method of claim 1 , wherein providing the substrate including a lower Si substrate and an insulating layer on the substrate and forming the projection comprises:
providing a Si substrate;
blanket depositing interleaved Si1−xGex and Si layers on the Si substrate;
etching the interleaved Si1−xGex and Si layers and the Si substrate to from the projection and form recesses in the Si substrate;
backfilling an insulation material at opposing side of the projection; and
recessing the insulation material to form the insulating layer.
4. The method of claim 1 , further comprising forming a nanowire transistor on the substrate comprising a high k gate dielectric, a metal gate, spacers, source and drain contacts, isolation regions and interconnects.
5. The method of claim 4 , further comprising forming a multilevel memory cell comprising a control gate, spacers, source, and drain contacts and interconnects.