Deep gate-all-around semiconductor device having germanium or group III-V active layer
View Patent ↗Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
1. A non-planar semiconductor device, comprising:
a hetero-structure disposed above a substrate, the hetero-structure comprising a hetero junction between an upper layer and a lower layer of differing composition;
an active layer disposed above the hetero-structure and having a composition different from the upper and lower layers of the hetero-structure;
a gate electrode stack disposed on and completely surrounding a channel region of the active layer, and disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure;
source and drain regions disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack; and
isolation regions adjacent the source and drain regions and disposed at least partially into the hetero-structure, wherein the gate electrode stack is disposed to a depth in the hetero-structure deeper than a depth of the isolation regions.
2. The non-planar semiconductor device of claim 1 , wherein the channel region of the active layer has a lower band gap than the lower layer, and the lower layer has a lower band gap than the upper layer.
3. The non-planar semiconductor device of claim 2 , wherein the channel region of the active layer consists essentially of germanium, the lower layer comprises Si x Ge 1-x , and the upper layer comprises Si y Ge 1-y , where 1>y>x>0.
4. The non-planar semiconductor device of claim 3 , wherein y is approximately 0.5, and x is approximately 0.3.
5. The non-planar semiconductor device of claim 2 , wherein the active layer, the lower layer, and the upper layer each comprise a different group III-V material.
6. The non-planar semiconductor device of claim 1 , wherein the gate electrode stack is disposed to a depth in the hetero-structure approximately 2-4 times a depth of the source and drain regions in the hetero-structure.
7. The non-planar semiconductor device of claim 1 , wherein the gate electrode stack comprises a high-k gate dielectric layer lining the trench, and a metal gate electrode within the high-k gate dielectric layer.
8. The non-planar semiconductor device of claim 1 , further comprising:
one or more nanowires disposed in a vertical arrangement above the active layer, wherein the gate electrode stack is disposed on and completely surrounds a channel region of each of the nanowires.
9. A method of fabricating a non-planar semiconductor device, the comprising:
forming a hetero-structure above a substrate, the hetero-structure comprising a hetero-junction between an upper layer and a lower layer of differing composition;
forming an active layer above the hetero-structure and having a composition different from the upper and lower layers of the hetero-structure;
forming a trench in the upper layer and at least partially in the lower layer;
forming a gate electrode stack on and completely surrounding a channel region of the active layer, and in the trench in the upper layer and at least partially in the lower layer;
forming source and drain regions in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack; and
forming, at least partially into the hetero-structure, isolation regions adjacent the source and drain regions, wherein the gate electrode stack is formed to a depth in the hetero-structure deeper than a depth of the isolation regions.
10. The method of claim 9 , wherein forming the trench in the upper layer and at least partially in the lower layer is performed subsequent to removal of a dummy gate structure in a replacement gate process.
11. The method of claim 9 , wherein the channel region of the active layer has a lower band gap than the lower layer, and the lower layer has a lower band gap than the upper layer.
12. The method of claim 11 , wherein the channel region of the active layer consists essentially of germanium, the lower layer comprises Si x Ge 1-x , and the upper layer comprises Si y Ge 1-y , where 1>y>x>0.
13. The method of claim 12 , wherein y is approximately 0.5, and x is approximately 0.3.
14. The method of claim 11 , wherein the channel region of the active layer, the lower layer, and the upper layer each comprise a different group III-V material.
15. The method of claim 9 , wherein the gate electrode stack is formed to a depth in the hetero-structure approximately 2-4 times a depth of the source and drain regions in the hetero-structure.
16. The method of claim 9 , wherein the gate electrode stack comprises a high-k gate dielectric layer lining the trench, and a metal gate electrode within the high-k gate dielectric layer.
17. The method of claim 9 , further comprising:
forming one or more nanowires in a vertical arrangement above the active layer, wherein the gate electrode stack is formed on and completely surrounds a channel region of each of the nanowires.
18. A non-planar semiconductor device, comprising:
a hetero-structure disposed above a substrate, the hetero-structure comprising a hetero junction between an upper layer and a lower layer of differing composition;
an active layer disposed above the hetero-structure and having a composition different from the upper and lower layers of the hetero-structure;
a gate electrode stack disposed on and completely surrounding a channel region of the active layer;
source and drain regions disposed in the active layer and in the upper layer on either side of the gate electrode stack; and
isolation regions adjacent the source and drain regions and disposed at least partially into the hetero-structure, wherein the gate electrode stack is disposed to a depth in the hetero-structure deeper than a depth of the isolation regions.
19. The non-planar semiconductor device of claim 18 , wherein the channel region of the active layer has a lower band gap than the lower layer, and the lower layer has a lower band gap than the upper layer.
20. The non-planar semiconductor device of claim 19 , wherein the channel region of the active layer consists essentially of germanium, the lower layer comprises Si x Ge 1-x , and the upper layer comprises Si y Ge 1-y , where 1>y>x>0.
21. The non-planar semiconductor device of claim 20 , wherein y is approximately 0.5, and x is approximately 0.3.
22. The non-planar semiconductor device of claim 19 , wherein the active layer, the lower layer, and the upper layer each comprise a different group III-V material.
23. The non-planar semiconductor device of claim 18 , wherein the gate electrode stack is disposed to a depth in the hetero-structure approximately 2-4 times a depth of the source and drain regions in the hetero-structure.
24. The non-planar semiconductor device of claim 18 , wherein the gate electrode stack comprises a high-k gate dielectric layer lining the trench, and a metal gate electrode within the high-k gate dielectric layer.
25. The non-planar semiconductor device of claim 18 , further comprising:
one or more nanowires disposed in a vertical arrangement above the active layer, wherein the gate electrode stack is disposed on and completely surrounds a channel region of each of the nanowires.