Group III-N nanowire transistors
View Patent ↗A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
1. A method of forming a group III-N transistor on a substrate, the method comprising:
epitaxially growing a stack of semiconductor materials on the substrate, the stack comprising at least a first group III-N material;
etching the stack to define a nanowire;
epitaxially growing a second group III-N material on the first group III-N material along a channel region of the nanowire; and
forming a gate conductor coaxially wrapping completely around the first semiconductor and over the second group III-N material, along a longitudinal channel length of the nanowire.
2. The method of claim 1 , wherein etching the stack further comprises removing a third semiconductor material selectively relative to the first group III-N material to form a gap between the first group III-N material and the substrate along the longitudinal channel length;
wherein epitaxially growing the second group III-N material further comprises growing the second group III-N material on a surface of the first group III-N material exposed by the gap; and
wherein forming gate conductor further comprises backfilling the gap with the gate insulator and gate conductor along the longitudinal channel length.
3. The method of claim 1 , wherein epitaxially growing the stack of semiconductor materials further comprises growing the first group III-N material on a third group III-N material, and wherein removing the third semiconductor material selectively to the first group III-N material further comprises removing the third group III-N material to undercut the first group III-N material.
4. The method of claim 3 , wherein epitaxially growing the first group III-N material further comprises epitaxially growing a material consisting essentially of GaN, or consisting essentially of InN, or consisting essentially of Al x In 1-x N, where x is less than 1, or consisting essentially of Al x Ga 1-x N, where x is less than 1; and
wherein epitaxially growing the third group III-N comprises epitaxially growing AlN, GaN, Al z In 1-z N, or AlzGa 1-z N, where z is different than x.
5. The method of claim 4 , wherein epitaxially growing the second group III-N material further comprises growing AlN, GaN, Al y In 1-y N, where y is greater than x, or Al y Ga 1-x N, where y is greater than x.
6. The method of claim 3 , further comprising:
thermal annealing at a temperature sufficient to intermix the first and third group III-N materials remaining as an epitaxial stack after forming the gate conductor.
7. The method of claim 1 , further comprising:
forming a drain contact coaxially wrapping completely around the first group III-N along a drain region of the nanowire; and
forming a source contact coaxially wrapping completely around the first group III-N along source region of the nanowire.
8. The method of claim 7 , wherein forming drain contact, and source contact, further comprises:
removing the third group III-N material selectively to the first group III-N material to form a second gap between the first group III-N and the substrate along each of the source and drain regions; and
backfilling the second gap with an ohmic metal.