Semiconductor device having self-aligned epitaxial source and drain extensions
View Patent ↗A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.
1. A transistor comprising:
a gate stack formed on a substrate;
spacers formed on laterally opposite sides of the gate stack;
a source region and a drain region formed in the substrate adjacent and subjacent to the spacers, wherein:
the source region includes a self-aligned source extension in close proximity to the gate stack of the transistor, wherein an interface between the source region and the substrate follows the <111> and <001> crystallographic planes, and
the drain region includes a self-aligned drain extension in close proximity to the gate stack of the transistor, wherein an interface between the drain region and the substrate follows the <111> and <001> crystallographic planes.
2. The transistor of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
3. The transistor of claim 1 , wherein the source region and the drain region comprise carbon doped silicon.
4. The transistor of claim 1 , wherein the source region and the drain region comprise boron doped silicon germanium.
5. The transistor of claim 2 , wherein the source extension overlaps the high-k gate dielectric layer by more than 10 nm from and the drain extension overlaps the high-k gate dielectric layer by more than 10 nm.
6. The transistor of claim 1 , wherein the source and drain extensions are epitaxially deposited.
7. The transistor of claim 1 , wherein the source and drain extensions are formed by doping portions the substrate, etching the doped portions, and epitaxially depositing a silicon containing material in the etched areas.