IP Library Granted Patent US 8,269,209
Granted Patent B2
US 8,269,209 · App. 12/653,847 · Granted Sep 18, 2012

Isolation for nanowire devices

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Quick Facts
Patent No.
US 8,269,209
App. No.
12/653,847
Granted
Sep 18, 2012
Kind
B2
Abstract

The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.

Claims (52)

1. A nanowire isolation structure formed by a method, comprising:

forming at least one nanowire;

forming a dielectric material adjacent to and in contact with the at least one nanowire, wherein forming the dielectric material includes forming at least one divot channel in the dielectric material;

forming a high-K dielectric protective layer over the dielectric material and the nanowire;

depositing a filler dielectric material over the protective layer; and

removing a portion of the filler dielectric material to expose a portion of the protective layer and to leave a portion of the filler dielectric material within the divot channel.

2. The nanowire isolation structure of claim 1 wherein removing the portion of the filler dielectric material to expose a portion of the protective layer and leave a portion of the filler dielectric within the divot channel comprises removing the portion of the filler dielectric material to expose a portion of the protective layer and leave a portion of the filler dielectric within the divot channel which is substantially planar to the protective layer.

3. The nanowire isolation structure of claim 1 wherein forming at least one nanowire comprises forming at least one germanium nanowire.

4. The nanowire isolation structure of claim 3 wherein forming as least one germanium nanowire comprises forming at least one germanium nanowire having a germanium content of between about 50 and 100%.

5. A nanowire isolation structure formed by a method, comprising:

forming at least one nanowire;

forming a dielectric material adjacent to and in contact with the at least one nanowire, wherein forming the dielectric material includes forming at least one divot channel in the dielectric material;

forming a silicon nitride protective layer over the dielectric material and the nanowire;

depositing a filler dielectric material over the protective layer; and

removing a portion of the filler dielectric material to expose a portion of the protective layer and to leave a portion of the filler dielectric material within the divot channel.

6. A nanowire isolation structure formed by a method, comprising:

forming at least one nanowire, wherein forming that at least one nanowire comprises:

patterning a mask on a substrate;

etching the substrate to form at least one recess and at least one fin, each fin having a top surface and two opposing sides;

removing the patterned mask;

depositing the dielectric material over the recesses and fins;

recessing the dielectric material to expose a portion of the sides of each fin;

forming a germanium alloy cladding on the exposed sides and the top surface of each fin; and oxidizing and annealing the germanium alloy cladding to convert the germanium alloy cladding into a germanium nanowire;

forming a dielectric material adjacent to and in contact with the at least one nanowire, wherein forming the dielectric material includes forming at least one divot channel in the dielectric material;

forming a protective layer over the dielectric material and the nanowire;

depositing a filler dielectric material over the protective layer; and

removing a portion of the filler dielectric material to expose a portion of the protective layer and to leave a portion of the filler dielectric material within the divot channel.

7. The nanowire isolation structure of claim 6 wherein patterning a mask on a substrate comprises patterning a mask on a silicon-containing substrate.

8. The nanowire isolation structure of claim 7 wherein forming the germanium alloy cladding comprises forming a silicon germanium alloy cladding.

9. A nanowire isolation structure formed by a method, comprising:

forming at least one nanowire;

forming a dielectric material adjacent to and in contact with the at least one nanowire, wherein forming the dielectric material includes forming at least one divot channel in the dielectric material;

wherein forming the at least one nanowire and forming the dielectric material adjacent the nanowire comprises:

forming the at least one recess and at least one fin in a silicon-containing substrate, each fin having a top surface and two opposing sides;

depositing the dielectric material over the recess and fin;

recessing the dielectric material to expose a portion of at least one side of the fin;

forming an alloy cladding on the exposed side and the top surface of each fin;

converting the alloy cladding into a nanowire and an oxide shell substantially surrounding the nanowire;

depositing a second dielectric material over the nanowire and dielectric material; and

removing the second dielectric material and the oxide shells;

forming a protective layer over the dielectric material and the nanowire;

depositing a filler dielectric material over the protective layer; and

removing a portion of the filler dielectric material to expose a portion of the protective layer and to leave a portion of the filler dielectric material within the divot channel.

10. The nanowire isolation structure of claim 5 wherein removing the portion of the filler dielectric material to expose a portion of the protective layer and leave a portion of the filler dielectric within the divot channel comprises removing the portion of the filler dielectric material to expose a portion of the protective layer and leave a portion of the filler dielectric within the divot channel which is substantially planar to the protective layer.

11. The nanowire isolation structure of claim 5 wherein forming at least one nanowire comprises forming at least one germanium nanowire.

12. The nanowire isolation structure of claim 11 wherein forming as least one germanium nanowire comprises forming at least one germanium nanowire having a germanium content of between about 50 and 100%.

13. The nanowire isolation structure of claim 6 wherein removing the portion of the filler dielectric material to expose a portion of the protective layer and leave a portion of the filler dielectric within the divot channel comprises removing the portion of the filler dielectric material to expose a portion of the protective layer and leave a portion of the filler dielectric within the divot channel which is substantially planar to the protective layer.

14. The nanowire isolation structure of claim 6 wherein forming at least one nanowire comprises forming at least one germanium nanowire.

15. The nanowire isolation structure of claim 11 wherein forming as least one germanium nanowire comprises forming at least one germanium nanowire having a germanium content of between about 50 and 100%.

16. The nanowire isolation structure of claim 9 wherein removing the portion of the filler dielectric material to expose a portion of the protective layer and leave a portion of the filler dielectric within the divot channel comprises removing the portion of the filler dielectric material to expose a portion of the protective layer and leave a portion of the filler dielectric within the divot channel which is substantially planar to the protective layer.

17. The nanowire isolation structure of claim 9 wherein forming at least one nanowire comprises forming at least one germanium nanowire.

18. The nanowire isolation structure of claim 17 wherein forming as least one germanium nanowire comprises forming at least one germanium nanowire having a germanium content of between about 50 and 100%.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2020
From: INTEL CORPORATION
To: GOOGLE LLC
Reel/Frame 054772/0918 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2011
From: SHAH, UDAY; CHU-KUNG, BENJAMIN; JIN, BEEN-YIH; PILLARISETTY, RAVI; RADOSAVLJEVIC, MARKO; RACHMADY, WILLY
To: INTEL CORPORATION
Reel/Frame 026666/0335 →