Fabrication of germanium nanowire transistors
View Patent ↗In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.
1. A method comprising:
forming an silicon fin surrounded by trench isolation regions in a semiconductor substrate;
forming a silicon germanium layer over the silicon fin;
forming oxide masking layers at two end regions of the silicon fins;
exposing the silicon germanium layer in middle region of the silicon fin to preferential silicon oxidation to form a germanium nanowire in the middle region of the silicon fin and silicon germanium pillar anchors at the two oxide masked end regions of the silicon fin;
forming an dielectric layer over the substrate;
forming a conducting layer over the dielectric layer; and
forming a polysilicon gate line.
2. The method of claim 1 , further comprising recess etching the trench isolation regions to expose foot of the silicon fin in the middle section of the fin where there is no oxide masking layer.
3. The method of claim 1 , wherein the exposing includes optimizing the silicon oxidation conditions to fully convert the silicon germanium layer over the middle region of the silicon fin into the germanium nanowire, while partially converting the silicon germanium layer at the two oxide masked end regions into the silicon germanium pillars, wherein the silicon germanium pillars contain a higher percentage of germanium than the silicon germanium layer.
4. The method of claim 1 , wherein
the forming an dielectric layer includes forming a high dielectric constant layer; and
the forming a conducting layer includes forming a metallic layer with work function matched to the Germanium nanowire.
5. The method of claim 1 , wherein the forming a polysilicon gate line includes
forming a sacrificial oxide layer over the substrate;
forming a trench in the sacrificial oxide layer over a channel region;
forming the polysilicon gate line within the trench; and
removing the sacrificial oxide layer.
6. The method of claim 1 , further comprising forming contacts in alignment with source/drain regions and the polysilicon gate line.
7. The method of claim 6 , wherein the forming contacts includes
forming an interlayer dielectric layer over the substrate;
etching contact holes in the interlayer dielectric layer in alignment with the source/drain regions and the polysilicon gate line; and
forming contact plugs within the contact holes.
8. The method of claim 1 , further comprising
removing the dielectric layer and the conducting layer from source/drain regions; and
forming a silicon germanium layer over the polysilicon gate line, the germanium nanowire in the source/drain regions, and the silicon germanium anchors.
9. A method comprising:
forming an silicon fin surrounded by trench isolation regions in a semiconductor substrate;
forming a silicon germanium layer over the silicon fin;
forming oxide masking layers at two end regions of the fin;
etching the trench isolation regions to expose foot of the silicon fin in middle region of the fin;
exposing the substrate to silicon oxidation to fully convert the silicon germanium layer in the middle region of the fin into a germanium nanowire, while partially converting the silicon germanium layer at the two oxide masked end regions into silicon germanium pillars, wherein the silicon germanium pillars contain a higher percentage of germanium than the silicon germanium layer;
forming a high dielectric constant layer over the germanium nanowire and the silicon germanium pillars;
forming a metal work function layer over the high dielectric constant layer;
forming a sacrificial oxide layer over the substrate;
forming a trench in the sacrificial oxide layer over a channel region; and
forming a polysilicon gate line within the trench.
10. The method of claim 9 , further comprising
removing the high dielectric constant layer and the metal work function layer from source/drain regions; and
forming a silicon germanium layer over the polysilicon gate line, the germanium nanowire in the source/drain regions and the silicon germanium anchors.
11. The method of claim 10 , further comprising
forming an interlayer dielectric layer over the substrate;
etching contact holes in the interlayer dielectric layer in alignment with the source/drain regions and the polysilicon gate line; and
forming contact plugs within the contact holes.
12. The method of claim 9 , further comprising implanting source/drain regions.
13. The method of claim 9 , further comprising silicide and germanide formation of source/drain regions and polysilicon gate line.