Wide-band high-gain limiting amplifier with parallel resistor-transistor source loads
View Patent ↗An amplifier has a wide bandwidth and a high gain by using parallel loads. Each load has a load resistor and a load p-channel transistor in parallel. The drain voltages of differential n-channel transistors can be set by the load resistors, while switching current is provided by the load p-channel transistors. The parallel load provides a high impedance to the drain nodes yet still provides driving current. A transconductance stage with a pair of differential transistors and two parallel loads drives a shunt-shunt-feedback stage that has another pair of differential transistors and two more parallel loads. Shunt resistors between the gate and drain of the differential transistors in the shunt-shunt-feedback stage provide shunt feedback and low impedance. Several pairs of transconductance and shunt-shunt-feedback stages can be cascaded together. The cascaded amplifier may be used as a signal repeater.
1. A wideband amplifier comprising:
a first differential input and a second differential input that are driven in opposite directions to carry data;
a transconductance stage that comprises:
a first differential transistor having a gate that receives the first differential input, the gate controlling current in a channel between a first inter-stage node and a first tail node;
a first load between a first supply and the first inter-stage node, the first load having a first resistor in parallel with a channel of a first load transistor;
a second differential transistor having a gate that receives the second differential input, the gate controlling current in a channel between a second inter-stage node and the first tail node;
a second load between the first supply and the second inter-stage node, the second load having a second resistor in parallel with a channel of a second load transistor;
a second stage that comprises:
a third differential transistor having a gate that receives the first inter-stage node, the gate controlling current in a channel between a first output node and a second tail node;
a third load between the first supply and the first output node, the third load having a third resistor in parallel with a channel of a third load transistor;
a fourth differential transistor having a gate that receives the second inter-stage node, the gate controlling current in a channel between a second output node and the second tail node; and
a fourth load between the first supply and the second output node, the fourth load having a fourth resistor in parallel with a channel of a fourth load transistor;
wherein the second stage further comprises:
a first shunt resistor coupled between the first inter-stage node and the first output node;
a second shunt resistor coupled between the second inter-stage node and the second output node,
whereby the second stage is a shunt-shunt-feedback stage and whereby the first, second, third, and fourth loads each have a resistor and a transistor in parallel.
2. The wideband amplifier of claim 1 further comprising:
a first tail transistor that conducts current from the first tail node to a second supply;
a second tail transistor that conducts current from the second tail node to the second supply.
3. The wideband amplifier of claim 2 wherein the first, second, third, and fourth differential transistors are n-channel transistors;
wherein the first, second, third, and fourth load transistors are p-channel transistors.
4. The wideband amplifier of claim 3 wherein the first supply is a power supply and the second supply is a ground.
5. The wideband amplifier of claim 4 wherein the first and second tail transistors are n-channel transistors.
6. The wideband amplifier of claim 5 wherein gates of the first, second, third, and fourth load transistors are driven by a first bias voltage.
7. The wideband amplifier of claim 6 wherein the first bias voltage is a voltage between the first supply and the second supply.
8. The wideband amplifier of claim 7 further comprising:
a bias generator, coupled between the first supply and the second supply, the bias generator generating the first bias voltage.
9. The wideband amplifier of claim 8 wherein gates of the first and second tail transistors are driven by a second bias voltage.
10. The wideband amplifier of claim 9 wherein the bias generator also generates the second bias voltage.
11. The wideband amplifier of claim 10 wherein a size of the first load transistor is less than half of a size of the first tail transistor;
wherein a size of the third load transistor is less than half of a size of the second tail transistor;
wherein a size of the second load transistor is a same size as the size of the first load transistor;
wherein a size of the fourth load transistor is a same size as the size of the third load transistor.
12. The wideband amplifier of claim 2 wherein the first supply is a ground and the second supply is a power supply;
wherein the first, second, third, and fourth differential transistors are p-channel transistors;
wherein the first, second, third, and fourth load transistors are n-channel transistors.
13. A multi-stage amplifier comprising:
a transconductance stage receiving a first differential input and a second differential input and driving a first differential intermediate node and a second differential intermediate node;
a shunt-shunt-feedback stage receiving the first differential intermediate node and the second differential intermediate node as inputs and driving a first differential output and a second differential output;
wherein the transconductance stage comprises:
a first differential transistor having a gate receiving the first differential input, a source connected to a first tail node, and a drain driving the first differential intermediate node;
a first load resistor connected between the first differential intermediate node and a first supply;
a first load transistor connected between the first differential intermediate node and the first supply and having a gate driven by a first bias voltage;
wherein the first load resistor and the first load transistor are connected in parallel;
a first tail transistor having a gate driven by a second bias voltage and a source connected to a second supply and a drain connected to the first tail node;
a second differential transistor having a gate receiving the second differential input, a source connected to the first tail node, and a drain driving the second differential intermediate node;
a second load resistor connected between the second differential intermediate node and the first supply;
a second load transistor connected between the second differential intermediate node and the first supply and having a gate driven by the first bias voltage;
wherein the second load resistor and the second load transistor are connected in parallel;
wherein the shunt-shunt-feedback stage comprises:
a third differential transistor having a gate receiving the first differential intermediate node, a source connected to a second tail node, and a drain driving the first differential output;
a third load resistor connected between the first differential output and the first supply;
a third load transistor connected between the first differential output and the first supply and having a gate driven by the first bias voltage;
wherein the third load resistor and the third load transistor are connected in parallel;
a fourth differential transistor having a gate receiving the second differential intermediate node, a source connected to the second tail node, and a drain driving the second differential output;
a fourth load resistor connected between the second differential output and the first supply;
a fourth load transistor connected between the second differential output and the first supply and having a gate driven by the first bias voltage;
wherein the fourth load resistor and the fourth load transistor are connected in parallel;
a second tail transistor having a gate driven by the second bias voltage and a source connected to the second supply and a drain connected to the second tail node;
a first feedback resistor connected between the first differential intermediate node and the first differential output; and
a second feedback resistor connected between the second differential intermediate node and the second differential output.
14. The multi-stage amplifier of claim 13 wherein the multi-stage amplifier comprises a plurality of stages in a cascade, each stage comprising the transconductance stage and the shunt-shunt-feedback stage;
whereby the multi-stage amplifier is cascaded.
15. The multi-stage amplifier of claim 14 further comprising:
an offset cancellation, having the first and second differential outputs of a last stage in the cascade as inputs, and driving a bias onto a first differential input and a second differential input to a first stage in the cascade.
16. The multi-stage amplifier of claim 13 wherein the first supply is a power supply and the second supply is a ground;
wherein the first, second, third, and fourth load transistors are p-channel transistors;
wherein the first, second, third, and fourth differential transistors are n-channel transistors.
17. An amplifier comprising:
a first differential input and a second differential input;
first differential transistor means for controlling a first current between a first intermediate node and a first tail node in response to the first differential input;
first resistor load means for supplying a current to the first intermediate node from a first supply in response to a voltage difference between the first supply and the first intermediate node;
first transistor load means for controlling a first load current between the first supply and the first intermediate node in response to a first bias voltage;
second differential transistor means for controlling a second current between a second intermediate node and the first tail node in response to the second differential input;
second resistor load means for supplying a current to the second intermediate node from the first supply in response to a voltage difference between the first supply and the second intermediate node;
second transistor load means for controlling a second load current between the first supply and the second intermediate node in response to the first bias voltage;
third differential transistor means for controlling a third current between a first differential output and a second tail node in response to the first intermediate node;
third resistor load means for supplying a current to the first differential output from the first supply in response to a voltage difference between the first supply and the first differential output;
third transistor load means for controlling a third load current between the first supply and the first differential output in response to the first bias voltage;
fourth differential transistor means for controlling a fourth current between a second differential output and the second tail node in response to the second intermediate node;
fourth resistor load means for supplying a current to the second differential output from the first supply in response to a voltage difference between the first supply and the second differential output;
fourth transistor load means for controlling a fourth load current between the first supply and the second differential output in response to the first bias voltage;
first feedback means for shunting current between the first differential output and the first intermediate node in response to a voltage difference between the first differential output and the first intermediate node; and
second feedback means for shunting current between the second differential output and the second intermediate node in response to a voltage difference between the second differential output and the second intermediate node.
18. The amplifier of claim 17 further comprising:
first current sink means for sinking a first sink current between the first tail node and a second supply; and
second current sink means for sinking a second sink current between the second tail node and a second supply.
19. The amplifier of claim 17 wherein a gain of the amplifier is at least 40 decibels when a frequency of the first and second differential inputs is one Gigahertz.