Clearance hole size adjustment for impedance control in multilayer electronic packaging and printed circuit boards
View Patent ↗The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the clearance hole; calculating a characteristic impedance for the at least one via; and adjusting at least a size of the clearance hole until the characteristic impedance for the at least one via is approximately equal to a desired characteristic impedance.
1. A method for impedance control, comprising:
providing parameters for a structure having a clearance hole and a pair of vias passing through the clearance hole;
calculating a characteristic impedance for the vias; and
iteratively adjusting a pitch of the vias, a size of the clearance hole, and at least one dimension of at least one of the vias, until the characteristic impedance for the vias is approximately equal to a desired characteristic impedance.
2. The method of claim 1 , wherein the structure is selected from the group consisting of an electronic package and a printed circuit board.
3. The method of claim 1 , wherein the structure is a multilayer structure.
4. A method for impedance control, comprising:
providing parameters for a structure having a clearance hole and a pair of vias passing through the clearance hole;
calculating a characteristic impedance for the vias; and
iteratively adjusting a pitch of the vias, a size of the clearance hole, and at least one dimension of at least one of the vias, until the characteristic impedance for the vias is approximately equal to a desired characteristic impedance;
wherein the pair of vias passing through the clearance hole form a differential connection, and wherein the desired characteristic impedance is approximately 100 Ohms.
5. A system for impedance control, comprising:
means for providing parameters for a structure having a clearance hole and a pair of vias passing through the clearance hole;
means for calculating a characteristic impedance for the vias; and
means for iteratively adjusting a pitch of the vias, a size of the clearance hole, and at least one dimension of at least one of the vias, until the characteristic impedance for the vias is approximately equal to a desired characteristic impedance.
6. The system of claim 5 , wherein the structure is selected from the group consisting of an electronic package and a printed circuit board.
7. The system of claim 5 , wherein the structure is a multilayer structure.
8. A system for impedance control, comprising:
means for providing parameters for a structure having a clearance hole and a pair of vias passing through the clearance hole;
means for calculating a characteristic impedance for the vias; and
means for iteratively adjusting a pitch of the vias, a size of the clearance hole, and at least one dimension of at least one of the vias, until the characteristic impedance for the vias is approximately equal to a desired characteristic impedance;
wherein the pair of vias passing through the clearance hole form a differential connection, and wherein the desired characteristic impedance is approximately 100 Ohms.
9. A method for impedance control, comprising:
calculating a characteristic impedance for a pair of vias passing through a clearance hole in a structure; and
iteratively adjusting a pitch of the vias, a size of the clearance hole, and at least one dimension of at least one of the vias, until the characteristic impedance for the vias is approximately equal to a desired characteristic impedance.
10. The method of claim 9 , wherein the structure is a multilayer structure.
11. A method for impedance control, comprising:
calculating a characteristic impedance for a pair of vias passing through a clearance hole in a structure; and
iteratively adjusting a pitch of the vias, a size of the clearance hole, and at least one dimension of at least one of the vias, until the characteristic impedance for the vias is approximately equal to a desired characteristic impedance;
wherein the pair of vias passing through the clearance hole form a differential connection, and wherein the desired characteristic impedance is approximately 100 Ohms.