Digital-to-analog converter and related level shifter thereof
View Patent ↗A digital-to-analog converter has a plurality of current cells. Each of the current cells has a level shifter and a current source. The level shifter connects to a first power terminal and a second power terminal to convert a first input signal and a second input signal into a first output signal and a second output signal. The current source has two cascaded MOS transistors connected to the first power terminal in series, a first MOS switch having a gate for receiving the first output signal, and a second MOS switch having a gate for receiving the second output signal. A voltage level of the first power terminal is greater than a voltage level of the second power terminal. When one of the current cells operates, one of the first MOS switch and the second MOS switch of the current source is turned on and operates in a saturation region.
1. A digital-to-analog converter (DAC) comprising a plurality of current cells, and each of the current cells comprising:
a level shifter connected to a first power terminal and a second power terminal for converting a first input signal and a second input signal into a first output signal and a second output signal, the level shifter comprising:
a first module for converting the first input signal into the first output signal having a first NMOS transistor coupled to the first power terminal and a first PMOS transistor coupled to the second power terminal; and
a second module for converting the second input signal into the second output signal having a second NMOS transistor coupled to the first power terminal and a second NMOS transistor coupled to the second power terminal; and
a current source connected to the first power terminal and the second power terminal, the current source comprising:
two cascaded MOS transistors connected to the first power terminal in series;
a first MOS switch having a gate connected to the first module for receiving the first output signal; and
a second MOS switch having a gate connected to the second module for receiving the second output signal;
wherein the first power terminal supplies a digital high voltage level and the second power terminal supplies a digital low voltage level.
2. The DAC of claim 1 wherein when one of the current cells operates, one of the first MOS switch and the second MOS switch of the current source is turned on and operates in a saturation region.
3. The DAC of claim 1 wherein the first MOS switch and the second switch are PMOS transistors.
4. The DAC of claim 1 wherein the first input signal and the second input signal are complementary signals, and the first output signal and the second output signal are complementary signals.
5. The DAC of claim 1 wherein a voltage level of the first power terminal is greater than a voltage level of the second power terminal, and a voltage gap between the first output signal and the second output signal is less than a voltage gap between the first power terminal and the second power terminal and greater than a voltage gap between the first input signal and the second input signal.
6. The DAC of claim 1 wherein when a voltage level of the first input signal is greater than a voltage level of the second input signal, a voltage level of the second output signal is greater than a voltage level of the second power terminal, and a difference between the voltage level of the second output signal and the voltage level of the second power terminal is greater than or equal to a absolute value of a threshold voltage of the second PMOS transistor.
7. The DAC of claim 1 wherein when a voltage level of the first input signal is less than a voltage level of the second input signal, a voltage level of the first output signal is greater than a voltage level of the second power terminal, and a difference between the voltage level of the first output signal and the voltage level of the second power terminal is greater than or equal to a absolute value of a threshold voltage of the first PMOS transistor.
8. A digital-to-analog converter (DAC) comprising a plurality of current cells, and each of the current cells comprising:
a level shifter connected to a first power terminal and a second power terminal for converting a first input signal and a second input signal into a first output signal and a second output signal, a voltage level of the first power terminal being greater than a voltage level of the second power terminal; and
a current source connected to the first power terminal and the second power terminal, the current source comprising:
two cascaded MOS transistors connected to the first power terminal in series;
a first MOS switch having a gate for receiving the first output signal; and
a second MOS switch having a gate for receiving the second output signal;
wherein when one of the current cells operates, one of the first MOS switch and the second MOS switch of the current source is turned on and operates in a saturation region,
wherein the first power terminal supplies a digital high level and the second power terminal supplies a digital low voltage level.
9. The DAC of claim 8 wherein the first MOS switch and the second switch are PMOS transistors.
10. The DAC of claim 8 wherein the first input signal and the second input signal are complementary signals, and the first output signal and the second output signal are complementary signals.
11. The DAC of claim 8 wherein the level shifter comprising:
a first module for converting the first input signal into the first output signal having a first NMOS transistor coupled to the first power terminal and a first PMOS transistor coupled to the second power terminal; and
a second module for converting the second input signal into the second output signal having a second NMOS transistor coupled to the first power terminal and a second PMOS transistor coupled to the second power terminal;
wherein a voltage gap between the first output signal and the second output signal is less than a voltage gap between the first power terminal and the second power terminal and greater than a voltage gap between the first input signal and the second input signal.
12. The DAC of claim 11 wherein when a voltage level of the first input signal is greater than a voltage level of the second input signal, a voltage level of the second output signal is greater than the voltage level of the second power terminal, and a difference between the voltage level of the second output signal and the voltage level of the second power terminal is greater than or equal to a absolute value of a threshold voltage of the second PMOS transistor.
13. The DAC of claim 11 wherein when a voltage level of the first input signal is less than a voltage level of the second input signal, a voltage level of the first output signal is greater than the voltage level of the second power terminal, and a difference between the voltage level of the first output signal and the voltage level of the second power terminal is greater than or equal to a absolute value of a threshold voltage of the first PMOS transistor.
14. A level shifter for converting a first input signal and a second input signal into a first output signal and a second output signal, the level shifter comprising:
a first module connected to a first power terminal and a second power terminal for converting the first input signal into the first output signal, the first module having a first NMOS transistor coupled to the first power terminal and a first PMOS transistor coupled to the second power terminal; and
a second module connected to the first power terminal and the second power terminal for converting the second input signal into the second output signal, the second module having a second NMOS transistor coupled to the first power terminal and a second PMOS transistor coupled to the second power terminal;
wherein the first power terminal supplies a digital high voltage level and the second power terminal supplies a digital low voltage level, a voltage gap between the first output signal and the second output signal is less than a voltage gap between the first power terminal and the second power terminal and greater than a voltage gap between the first input signal and the second input signal.
15. The level shifter of claim 14 wherein the first input signal and the second input signal are complementary signals, and the first output signal and the second output signal are complementary signals.
16. The level shifter of claim 14 wherein when a voltage level of the first input signal is greater than a voltage level of the second input signal, a voltage level of the second output signal is greater than the voltage level of the second power terminal, and a difference between the voltage level of the second output signal and the voltage level of the second power terminal is greater than or equal to a absolute value of a threshold voltage of the second PMOS transistor.
17. The level shifter of claim 14 wherein when a voltage level of the first input signal is less than a voltage level of the second input signal, a voltage level of the first output signal is greater than the voltage level of the second power terminal, and a difference between the voltage level of the first output signal and the voltage level of the second power terminal is greater than or equal to a absolute value of a threshold voltage of the first PMOS transistor.
18. The DAC of claim 1 wherein the second power terminal supplies a ground voltage level.
19. The DAC of claim 8 wherein the second power terminal supplies a ground voltage level.
20. The level shifter of claim 14 wherein the second power terminal supplies a ground voltage level.