Trench capacitor of a DRAM and fabricating method thereof
View Patent ↗A method of fabricating trench capacitors is described. A substrate having at least one isolation structure is provided. A first trench and a second trench are formed in the substrate beside the isolation structure. A first lower electrode and a second lower electrode are formed in the substrate around the first trench and the second trench. A first capacitor dielectric layer and a second capacitor dielectric layer are formed on the respective surfaces of the first trench and the second trench. A first upper electrode and a second upper electrode are formed to fill the first trench and the second trench. A portion of the isolation structure between the first trench and the second trench is removed to form an opening. A conductive layer is formed to fill the opening and connect electrically with the first upper electrode and the second upper electrode.
1. A method of fabricating trench capacitors, comprising the steps of:
providing a substrate having at least an isolation structure formed thereon;
forming a first trench and a second trench in the substrate beside the isolation structure and removing a portion of the isolation structure between the first trench and the second trench to form an opening;
forming a first lower electrode and a second lower electrode in the substrate around the first trench and the second trench respectively;
forming a first capacitor dielectric layer and a second capacitor dielectric layer on the respective surfaces of the first trench and the second trench; and
filling the first trench, the second trench and the opening with a conductive material to form a first upper electrode, a second upper electrode and a conductive layer, wherein the first upper electrode and the second upper electrode are electrically connected through the conductive layer.
2. The method of claim 1 , wherein after forming the first upper electrode, the second upper electrode and the conductive layer. tbrther includes forming a contact on the conductive layer.
3. The method of claim 1 , wherein after forming the first upper electrode, the second upper electrode and the conductive layer, further includes forming a first contact and a second contact on the first upper electrode and the second upper electrode respectively.
4. The method of claim 1 , wherein the step of removing a portion of the isolation structure between the first trench and the second wench includes performing an etching operation.
5. The method of claim 1 , wherein the first trench and the second trench penetrate through the isolation structure.
6. The method of claim 1 , wherein the steps for fanning the first lower electrode and the second lower electrode include:
forming a doped insulating layer on the respective surfaces of the first trench and the second trench; and
performing a thermal treatment.
7. The method of claim 6 , wherein the material constituting the doped insulating layer comprises an arsenic-doped silicon oxide layer or a boron-doped silicon oxide layer.
8. The method of claim 1 , wherein the first capacitor dielectric layer and the second capacitor dielectric layer comprise a silicon oxide layer or an oxide/nitride/oxide stack layer.