Semiconductor structure and fabricating method thereof
View Patent ↗A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each dielectric layer. The metal patterns disposed in each dielectric layer extend to the next underlying dielectric layer.
1. A semiconductor structure, including:
a wafer having a chip area and a scribe line around the chip area;
a first dielectric layer and a second dielectric layer, sequentially disposed on the scribe line, wherein the first and second dielectric layers have a first interface therebetween; and
a first metal pattern, disposed passing through the second dielectric layer, the first interface and a portion of the first dielectric layer but not passing through the whole first dielectric layer,
wherein the first metal pattern has a first part and a second part, the second part is under the first part, and a width of the first part is the same to or greater than that of the second part.
2. The semiconductor structure as claimed in claim 1 , wherein a material of the first metal pattern is copper.
3. The semiconductor structure as claimed in claim 1 , wherein a material of the first and second dielectric layers is a low-k dielectric material.
4. The semiconductor structure as claimed in claim 3 , wherein the low-k dielectric material is fluorosilicate glass (FSG).
5. The semiconductor structure as claimed in claim 1 , further comprising:
a third dielectric layer disposed on the second dielectric layer, wherein the second and third dielectric layers have a second interface therebetween; and
a second metal pattern, disposed passing through third dielectric layer, the second interface, the second dielectric layer, the first interface and a portion of the first dielectric layer but not passing through the whole first dielectric layer.
6. A fabrication method of semiconductor structure, including
providing a wafer having a chip area and a scribe line around the chip area;
forming a first dielectric layer on the wafer;
forming a second dielectric layer on the first dielectric layer, wherein the first and second dielectric layer has a first interface therebetween; and
forming a first metal pattern passing through the second dielectric layer, the first interface and a portion of the first dielectric layer but not passing through the whole first dielectric layer,
wherein the step of forming the first metal pattern includes;
forming a trench in the second dielectric layer;
forming an opening in the second dielectric layer under the trench, wherein the opening extends into a portion of the first dielectric layer; and filling a metal material in the trench and opening.
7. The fabrication method of semiconductor structure as claimed in claim 6 , wherein a material of the first metal pattern is copper.
8. The fabrication method of semiconductor structure as claimed in claim 6 , wherein a material of the first dielectric layer is a low-k dielectric material.
9. The fabrication method of semiconductor structure as claimed in claim 8 , wherein the low-k dielectric material is fluorosilicate glass (FSG).
10. The fabrication method of semiconductor structure as claimed in claim 6 , wherein a material of the second dielectric layer is a low-k dielectric material.
11. The fabrication method of semiconductor structure as claimed in claim 10 , wherein the low-k dielectric material is fluorosilicate glass (FSG).
12. The fabrication method of semiconductor structure as claimed in claim 6 , further comprising:
forming a third dielectric layer on the second dielectric layer, wherein the second and third dielectric layers have a second interface therebetween; and
forming a second metal pattern passing through third dielectric layer, the second interface, the second dielectric layer, the first interface and a portion of die first dielectric layer but not passing through the whole first dielectric layer.
13. A fabrication method of semiconductor structure, including
providing a wafer having a chip area and a scribe line around the chip area;
forming a first dielectric layer on the wafer;
forming a second dielectric layer on the first dielectric layer, wherein the first and second dielectric layer has a first interface therebetween; and
forming a first metal pattern passing through the second dielectric layer, the first interface and a portion of the first dielectric layer but not passing through the whole first dielectric layer,
wherein the step of forming the first metal pattern includes:
forming an opening in the second dielectric layer, and the opening extends into a portion of the first dielectric layer;
forming a trench in the second dielectric layer above the opening; and
filling a metal material in the trench and opening.
14. The fabrication method of semiconductor structure as claimed in claim 13 , wherein a material of the first metal pattern is copper.
15. The fabrication method of semiconductor structure as claimed in claim 13 , wherein a material of the first dielectric layer is a low-k dielectric material.
16. The fabrication method of semiconductor structure as claimed in claim 15 , wherein the low-k dielectric material is fluorosilicate glass (FSG).
17. The fabrication method of semiconductor structure as claimed in claim 13 , wherein a material of the second dielectric layer is a low-k dielectric material.
18. The fabrication method of semiconductor structure as claimed in claim 17 , wherein the low-k dielectric material is fluorosilicate glass (FSG).
19. The fabrication method of semiconductor structure as claimed in claim 13 , comprising:
forming a third dielectric layer on the second dielectric layer, wherein the second and third dielectric layers have a second interface therebetween; and
forming a second metal pattern passing through third dielectric layer, the second interface, the second dielectric layer, the first interface and a portion of the first dielectric layer but not passing through the whole first dielectric layer.