High speed data bit latch circuit
View Patent ↗A latching circuit having a clock signal input and a data input, includes an inverting delay circuit having an input connected to DATA IN and having an output signal s 1 , a NAND circuit having a first input connected to signal s 1 , a second input connected to the clock signal, and an output signal s 2 , an OR circuit having a first input connected to the data input, a second input connected to s 2 , and an output signal s 3 , and a FLIP-FLOP circuit whose first input is connected to s 2 , whose second input connected to s 3 , and whose output is OUT Q.
1. An electronic latching circuit having inputs comprising a clock CLK signal and an input signal DATA IN, the circuit comprising:
(a) an inverting delay circuit, having an input connected to CLK and having an output signal s 1 whose output signal is inverted and delayed from CLK;
(b) a NAND circuit comprising a first input connected to signal s 1 , a second input connected to the clock signal, and an output signal s 2 ;
an OR circuit comprising a first input connected to DATA IN, a second input connected to s 2 , and an output signal s 3 , and
a FLIP-FLOP circuit comprising a first input connected to s 2 , and a second input connected to s 3 , and an output signal OUT Q.
2. The electronic latching circuit of claim 1 , wherein the inverting delay circuit comprises a delay of at least three time increments each equal to tD, and wherein the NAND circuit, the OR circuit, and each element of the FLIP-FLOP circuit each have a delay equal to tD.
3. The electronic latching circuit of claim 2 , wherein the clock CLK signal is periodic, and has a period of at least 12 tD.
4. The electronic latching circuit of claim 3 , wherein the inverting delay circuit further comprises three inverters connected in series.
5. The electronic latching circuit of claim 4 , wherein the flip-flop circuit further comprises two NAND gates, each comprising a first and second input and an output, an wherein:
(a) the first input of the first NAND gate is connected to signal 4 c;
(b) the second input of the first NAND gate is connected to the output of the second NAND gate;
(c) the first input of the second NAND gate is connected to the output of the first NAND gate; and
(d) the second input of the second NAND gate is connected to signal 7 c.
6. The electronic latching circuit of claim 2 , wherein the inverting delay circuit further comprises three inverters connected in series.
7. The electronic latching circuit of claim 6 , wherein the flip-flop circuit further comprises two NAND gates, each comprising a first and second input and an output, an wherein:
(a) the first input of the first NAND gate is connected to signal 4 c;
(b) the second input of the first NAND gate is connected to the output of the second NAND gate;
(c) the first input of the second NAND gate is connected to the output of the first NAND gate; and
(d) the second input of the second NAND gate is connected to signal 7 c.