Semiconductor structure and method of manufacture

1. A structure comprising a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness;

a reachthrough structure extending from the first subcollector to an upper surface of the second region

shallow trench isolation regions formed in the second region;

a P+ film formed over the upper surface of the second region and the shallow trench isolation regions;

an interlevel dielectric layer formed over the P+ film; and

a metal contact disposed in the interlevel dielectric layer, over the P+ film, and in contact with the P+ film,

wherein the reachthrough structure is arranged over the first subcollector and in contact with the first subcollector.

2. The structure of claim 1 , wherein the first subcollector forms a high breakdown voltage device.

3. The structure of claim 2 , wherein the second subcollector forms a high performance NPN device.

4. The structure of claim 2 , wherein the high breakdown voltage device is a PIN diode.

5. The structure of claim 2 , wherein the high breakdown voltage device is one of a NPN HBT transistor, varactor, passive, and schottky diode.

6. The structure of claim 1 , further comprising deep trench isolation regions formed in the second region.

7. The structure of claim 6 , wherein the deep trench isolation regions extend through the second region, through the first region, and into the substrate.

8. The structure of claim 1 , wherein other metal contacts extend to the reachthrough contacting the first subcollector.

9. The structure of claim 8 , wherein the other metal contacts extending to the reachthrough contacting the first subcollector form an N+ terminal.

10. The structure of claim 1 , wherein the thickness of the first region is a range of approximately from 1 um to 3 um.

11. The structure of claim 1 , wherein the thickness of the second region is approximately 0.3 to 1 um.

12. The structure of claim 1 , wherein the metal contact contacting the P+ film forms a P+ contact.

13. A multicircuit structure, comprising:

a far side subcollector formed in the first region having a first thickness;

a near side subcollector formed in the second region, the second region having a thickness less than that of a thickness of the first region;

a reachthrough structure extending from the far side subcollector to an upper surface of the second region;

a P+ film formed over the upper surface of the second region; and

a metal contact formed over the P+ film,

wherein the far side subcollector forms a high breakdown voltage device and the near side subcollector forms a high performance NPN device, and

the reachthrough structure is arranged over the first subcollector and in contact with the first subcollector.

14. The structure of claim 13 , further comprising isolation regions formed in the second region, wherein selective of the isolation regions extend into an underlying substrate through the first region and the second region.

15. The structure of claim 14 , wherein the metal contact contacting the P+ film forms a P+ anode.

16. The structure of claim 13 , wherein other metal contacts extending to the reachthrough contacting the far side subcollector form an N+ cathode.

17. The structure of claim 13 , wherein the high breakdown voltage device is a high breakdown NPN HBT, PIN diode, a varactor, passive, or schottky diode.

18. The structure of claim 13 , wherein the thickness of the first region is a range of approximately from 1 um to 3 um.

19. The structure of claim 13 , wherein the thickness of the second region is approximately from 0.3-1 um.

20. A semiconductor structure, comprising:

a substrate comprising a first subcollector;

a first epitaxial layer on the substrate and comprising a second subcollector;

a second epitaxial layer on the first epitaxial layer;

a first reachthrough formed over and in contact with the first subcollector, and extending from an upper surface of the second epitaxial layer to the first subcollector;

a second reachthrough extending from the upper surface of the second epitaxial layer to the second subcollector; and

a metal contact formed over the first reachthrough,

wherein the first reachthrough provides a conducting channel between the metal contact and the first subcollector.

21. The semiconductor structure of claim 20 , wherein the first subcollector forms a high breakdown voltage device and the second subcollector forms a high performance NPN device.

22. The semiconductor structure of claim 21 , wherein:

the thickness of the first epitaxial layer is a range of approximately from 1 um to 3 um, and

the thickness of the second epitaxial layer is a range of approximately from 0.3 um to 1 um.

23. The semiconductor structure of claim 22 , further comprising a deep trench isolation disposed between the first subcollector and the second subcollector, wherein the deep trench isolation extends through the second epitaxial layer, through the first epitaxial layer, and into the substrate.

24. The semiconductor device of claim 23 , further comprising:

a P+ film formed over the upper surface of the second epitaxial layer;

an interlevel dielectric layer formed over the upper surface of the second epitaxial layer; and

a second metal contact formed within the interlevel dielectric layer and contacting the P+ film.