IP Library Assignment 027991/0473
Patent Assignment
Reel/Frame 027991/0473

Assignment of Assignor's Interest

Recorded: 2012-04-04 Pages: 19
Assignor
Assignee
FACEBOOK, INC.
1601 WILLOW ROAD, MENLO PARK, CALIFORNIA, 94025
Covered Properties (51)
Mechanism for Executing Nested Transactions in an Execution Environment Supporting Flat Transactions Only
Patent: 7,346,632 →
Application: 10/055,208 →
Publication: US 2002/0161815
Article, Method, System and Apparatus for Decentralized Creation, Distribution, Verification and Transfer of Valuable Documents
Patent: 7,353,398 →
Application: 10/156,929 →
Publication: US 2003/0226028
Rule Based Engine for Validating Financial Transactions
Patent: 7,398,237 →
Application: 10/178,439 →
Publication: US 2003/0084428
Optimizing Source Code for Iterative Execution
Patent: 7,340,733 →
Application: 10/314,094 →
Publication: US 2003/0115579
Method of Comparing Documents Possessed by Two Parties
Patent: 7,337,319 →
Application: 10/621,731 →
Publication: US 2004/0111617
System and Method for Setting Special Wholesale Pricing for Resellers
Patent: 7,401,055 →
Application: 10/686,750 →
Publication: US 2005/0086181
Remote Bist High Speed Test and Redundancy Calculation
Patent: 7,401,281 →
Application: 10/707,971 →
Publication: US 2005/0172194
Cyclic Redundancy Check Generation Circuit
Patent: 7,328,396 →
Application: 10/709,794 →
Publication: US 2005/0268209
Error Correcting Logic System
Patent: 7,336,102 →
Application: 10/710,641 →
Publication: US 2006/0026457
System and Method for Addressing Inefficient Query Processing
Patent: 7,376,638 →
Application: 10/746,961 →
Publication: US 2005/0165741
Method for Adjusting Lithographic Mask Flatness Using Thermally Induced Pellicle Stress
Patent: 7,355,680 →
Application: 10/905,453 →
Publication: US 2006/0146313
Multiple Layer and Crystal Plane Orientation Semiconductor Substrate
Patent: 7,348,610 →
Application: 10/906,557 →
Publication: US 2006/0186416
Method and System for Configuring a Dependency Graph for Dynamic by-Pass Instruction Scheduling
Patent: 7,392,516 →
Application: 10/912,482 →
Publication: US 2006/0031823
Content Filtering, Ordering by Relevance, and Caching
Patent: 7,353,235 →
Application: 10/921,444 →
Publication: US 2005/0097121
Online Incremental Deferred Integrity Processing and Maintenance of Rolled in and Rolled Out Data
Patent: 7,359,923 →
Application: 10/923,547 →
Publication: US 2006/0041569
Method for Implementing Single Threaded Optimizations in a Potentially Multi-Threaded Environment
Patent: 7,395,530 →
Application: 10/930,032 →
Publication: US 2006/0048116
Method, System and Program Product for Displaying a Logical Structure
Patent: 7,389,296 →
Application: 10/932,676 →
Publication: US 2006/0047688
Parameter Management Using Compiler Directives
Patent: 7,367,019 →
Application: 10/942,428 →
Publication: US 2006/0059472
Fast/Slow State Machine Latch
Patent: 7,331,021 →
Application: 11/163,750 →
Publication: US 2007/0101304
Semiconductor Structure and Method of Manufacture
Patent: 7,329,940 →
Application: 11/163,882 →
Publication: US 2007/0096257
System and Method for Testing Pattern Sensitive Algorithms for Semiconductor Design
Patent: 7,353,472 →
Application: 11/202,591 →
Publication: US 2007/0038970
Balanced Sense Amplifier Circuits with Adjustable Transistor Body Bias
Patent: 7,333,379 →
Application: 11/275,539 →
Publication: US 2007/0159899
Frequency Divider Monitor of Phase Lock Loop
Patent: 7,362,184 →
Application: 11/276,410 →
Publication: US 2007/0200634
Multi-Arm Disk Drive System Having Interleaved Read/Write Operations and Method of Controlling Same
Patent: 7,385,781 →
Application: 11/278,283 →
Publication: US 2008/0123213
Method for Reducing Within Chip Device Parameter Variations
Patent: 7,393,703 →
Application: 11/382,489 →
Publication: US 2007/0264729
Circuit and Method for on-Chip Jitter Measurement
Patent: 7,339,364 →
Application: 11/424,881 →
Publication: US 2008/0012549
Method and Apparatus for Impedance Matching in Transmission Circuits Using Tantalum Nitride Resistor Devices
Patent: 7,345,503 →
Application: 11/427,798 →
Publication: US 2008/0001620
Shallow Trench Isolation Formation
Patent: 7,348,634 →
Application: 11/445,786 →
Publication: US 2006/0220148
Circuit and Method to Measure Threshold Voltage Distributions in Sram Devices
Patent: 7,352,252 →
Application: 11/456,684 →
Publication: US 2008/0024232
Frequency Divider Monitor of Phase Lock Loop
Patent: 7,627,835 →
Application: 11/765,475 →
Publication: US 2007/0245271
Error Correcting Logic System
Patent: 7,642,813 →
Application: 11/850,857 →
Publication: US 2009/0002015
Shallow Trench Isolation Formation
Patent: 7,652,334 →
Application: 11/866,471 →
Publication: US 2008/0017932
Fast/Slow State Machine Latch
Patent: 7,459,936 →
Application: 11/869,988 →
Publication: US 2008/0024166
Multiphase Divider for P-Pll Based Serial Link Receivers
Patent: 7,323,913 →
Application: 11/871,578 →
Semiconductor Structure and Method of Manufacture
Patent: 8,022,496 →
Application: 11/873,696 →
Publication: US 2008/0099787
Circuit and Method for on-Chip Jitter Measurement
Patent: 8,126,041 →
Application: 11/874,960 →
Publication: US 2009/0102452
Mechanism for Executing Nested Transactions in an Execution Environment Supporting Flat Transactions Only
Patent: 8,090,697 →
Application: 11/925,951 →
Publication: US 2008/0059965
Error Correcting Logic System
Patent: 7,471,115 →
Application: 11/926,386 →
Publication: US 2008/0048711
Method and Apparatus for Impedance Matching in Transmission Circuits Using Tantalum Nitride Resistor Devices
Patent: 7,378,866 →
Application: 11/942,396 →
Publication: US 2008/0061902
Testing Pattern Sensitive Algorithms for Semiconductor Design
Patent: 7,685,544 →
Application: 11/947,254 →
Publication: US 2008/0104555
Multiphase Divider for P-Pll Based Serial Link Receivers
Patent: 7,378,885 →
Application: 11/959,069 →
Multiple Layer and Crystal Plane Orientation Semiconductor Substrate
Patent: 7,521,735 →
Application: 11/969,320 →
Publication: US 2008/0099844
Comparison of Documents Possessed by Two Parties
Patent: 8,032,747 →
Application: 12/015,536 →
Publication: US 2008/0141030
Article and System for Decentralized Creation, Distribution, Verification and Transfer of Valuable Documents
Patent: 7,818,812 →
Application: 12/018,176 →
Publication: US 2008/0184337
Method for Adjusting Lithographic Mask Flatness Using Thermally Induced Pellicle Stress
Patent: 7,826,038 →
Application: 12/029,506 →
Publication: US 2008/0131795
Hybrid Built-in Self Test (Bist) Architecture for Embedded Memory Arrays and an Associated Method
Patent: 7,631,236 →
Application: 12/057,405 →
Publication: US 2008/0178053
A Method for Segmenting Bist Functionality in an Embedded Memory Array into Remote Lower-Speed Executable Instructions and Local Higher-Speed Executable Instructions
Patent: 7,472,325 →
Application: 12/062,599 →
Publication: US 2008/0215937
Methods for Reducing Within Chip Device Parameter Variations
Patent: 7,541,613 →
Application: 12/117,014 →
Publication: US 2008/0246097
System and Program Product for Displaying a Logical Structure
Patent: 7,877,416 →
Application: 12/118,155 →
Publication: US 2008/0288514
Rule Based Engine for Validating Financial Transactions
Patent: 8,001,525 →
Application: 12/118,799 →
Publication: US 2008/0250411
Multi-Arm Disk Drive System Having Interleaved Read/Write Operations and Method of Controlling Same
Patent: 7,710,683 →
Application: 12/127,108 →
Publication: US 2008/0225431
Related Assignments (3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 2, 2008
From: BERNSTEIN,KERRY; EMMA, PHILIP G.; FIFIELD, JOHN A.; KARTSCHOKE, PAUL D.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020345/0682 →
Change of Name Dec 20, 2021
From: FACEBOOK, INC.
To: META PLATFORMS, INC.
Reel/Frame 058553/0802 →
Change of Name Feb 25, 2022
From: FACEBOOK, INC.
To: META PLATFORMS, INC.
Reel/Frame 059251/0501 →