Error correcting logic system
View Patent ↗The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
1. An error correcting logic system comprising:
first means for outputting one of a first logic state and a second logic state, the second logic state being output in response to a logic input signal;
second means for outputting one of the first logic state and the second logic state, the second logic state being output in response to the logic input signal; and
third means for interconnecting outputs of the first means and the second means, and for correcting a fault by outputting the second logic state only when both the first means and the second means output the second logic state,
wherein the third means includes a NOR gate; wherein the first and second logic state includes a combinatorial logic section and a pre-charge section having a pre-charge device and a keeper device such that an output of the NOR gate feeds back to the keeper device.
2. A method for correcting a fault in a logic system, the method comprising:
providing a first dynamic logic gate;
providing a second dynamic logic gate that is redundant to the first dynamic logic gate;
combining outputs of the first and second dynamic logic gates to correct a fault in one of the first dynamic logic gate and the second dynamic logic gate, the combining including interconnecting outputs of the first and second dynamic logic gates with a NOR gate; and
providing a combinatorial logic section and a pre-charge section in each of the first and second dynamic logic gates, the combinatorial logic section and the pre-charge section connecting to form a critical node, the pre-charge section including a pre-charge device and a keeper device,
wherein the critical node is maintained at a high level charge through the keeper device and the output of the NOR gate feeds back to the keeper device.
3. The method of claim 2 , wherein the combining includes interconnecting outputs of the first and second dynamic logic gates with an AND gate.
4. The method of claim 3 , wherein the AND gate includes a NAND gate coupled to an inverting gate.
5. The method of claim 2 , wherein the combining includes interconnecting outputs of the first and second dynamic logic gates with a NOR gate.
6. The method of claim 2 , wherein each dynamic logic gate is a cascode voltage switch.
7. The method of claim 2 , wherein the fault is a soft error.
8. The method of claim 2 , wherein the combining includes interconnecting outputs of the first and second dynamic logic gates with a static gate.