Circuit and method for on-chip jitter measurement
View Patent ↗Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.
1. A method of measuring clock signal jitter, said method comprising:
receiving a clock signal from an on-chip phase locked loop;
dividing a frequency of said clock signal by two in order to produce a feedback clock signal;
coarsely tuning a circuit using a delay locked loop, said coarsely tuning comprising delaying said clock signal until a delayed clock signal with a predetermined phase shift from said clock signal is achieved and locking in said delayed clock signal such that said clock signal and said delayed clock signal are out of phase, said predetermined phase shift comprising a one-half cycle delay and said clock signal being two times said feedback clock signal providing for said one-half cycle delay to be sufficient to allow for a cycle-to-cycle jitter measurement;
finely tuning said circuit using a Vernier delay line, said finely tuning comprising acquiring data indicating phase differences between said clock signal and said delayed clock signal; and
processing said data to measure cycle-to-cycle jitter of said clock signal.
2. The method of claim 1 , said coarsely tuning further comprising incrementally delaying said clock signal until said predetermined phase shift is achieved.
3. The method of claim 1 , further comprising calibrating said circuit based on identical delay elements in said delay locked loop and said Vernier delay line.
4. The method of claim 1 , further comprising:
using said Vernier delay line to acquire additional data indicating phase differences between said feedback clock signal and a reference clock signal; and
processing said additional data and to measure phase jitter between said reference clock signal and said feedback clock signal.
5. A method of measuring clock signal jitter, said method comprising:
receiving a clock signal from an on-chip phase locked loop;
dividing a frequency of said clock signal by two in order to produce a feedback clock signal;
coarsely tuning a circuit using a delay locked loop, said coarsely tuning comprising delaying said clock signal until a delayed clock signal with a predetermined phase shift from said clock signal is achieved and locking in said delayed clock signal such that said clock signal and said delayed clock signal are out of phase, said predetermined phase shift comprising a one-half cycle delay and said clock signal being two times said feedback clock signal providing for said one-half cycle delay to be sufficient to allow for a cycle-to-cycle jitter measurement;
finely tuning said circuit using a Vernier delay line, said finely tuning comprising acquiring data indicating phase differences between said clock signal and said delayed clock signal;
processing said data to measure cycle-to-cycle jitter of said clock signal;
calibrating said circuit based on identical delay elements in said delay locked loop and said Vernier delay line;
using said Vernier delay line to acquire additional data indicating phase differences between said feedback clock signal and said a reference clock signal; and
processing said additional data and to measure phase jitter between said reference clock signal and said feedback clock signal.
6. The method of claim 5 , said coarsely tuning further comprising incrementally delaying said clock signal until said predetermined phase shift is achieved.
7. A method of measuring clock signal jitter, said method comprising:
receiving a clock signal from an on-chip phase locked loop;
dividing a frequency of said clock signal by two in order to produce a feedback clock signal;
coarsely tuning a circuit using a delay locked loop, said coarsely tuning comprising delaying said clock signal until a delayed clock signal with a predetermined phase shift from said clock signal is achieved and locking in said delayed clock signal such that said clock signal and said delayed clock signal are out of phase;
finely tuning said circuit using a Vernier delay line, said finely tuning comprising acquiring data indicating phase differences between said clock signal and said delayed clock signal;
processing said data to measure cycle-to-cycle jitter of said clock signal;
calibrating said circuit based on identical delay elements in said delay locked loop and said Vernier delay line;
using said Vernier delay line to acquire additional data indicating phase differences between said feedback clock signal and said a reference clock signal; and
processing said additional data and to measure phase jitter between said reference clock signal and said feedback clock signal.