Method and apparatus for impedance matching in transmission circuits using tantalum nitride resistor devices

1. A method for trimming impedance matching devices in high-speed circuits, the method comprising:

determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test;

comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter;

altering the resistance value of the first TaN resistor by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor;

determining whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof; and

repeating the altering of the resistance value of the first TaN resistor by application of a trimming voltage until the electrical parameter equals the desired design value thereof.

2. The method of claim 1 , further comprising trimming the value of a second TaN resistor included within the circuit in the same manner as the first TaN resistor, wherein the first and second TaN resistors are included in a differential driver portion of the circuit.

3. The method of claim 2 , wherein:

the electrical parameter of the TaN resistors is the impedance thereof;

the impedance of the first and second TaN resistors are individually measured through an ohmmeter included within an external testing device with respect to a chip on which the circuit under test is formed, and while the individual TaN resistor being measured is electrically isolated from a voltage supply bus of the circuit under test; and

the trimming voltage used to individually alter the resistance value of the first and second TaN resistors is applied through a variable voltage source included within the external testing device.

4. The method of claim 3 , wherein the circuit under test further comprises a plurality of PFET switching devices configured to selectively couple and decouple the first and second TaN resistors to and from the voltage supply bus and a pin accessible by the external testing device.

5. The method of claim 2 , wherein:

the electrical parameter of the TaN resistors is the impedance thereof;

the impedance of the first and second TaN resistors are individually determined through a voltage measurement thereacross by a voltmeter included within an external testing device with respect to a chip on which the circuit under test is formed, and in combination with a variable current source included within the testing device, the variable current source configured to supply current individually through the first and second TaN resistors; and

wherein the variable current source is also configured to generate a level of current sufficient to correspond to the trimming voltage used to individually alter the resistance value of the first and second TaN resistors.

6. The method of claim 2 , wherein:

the electrical parameter of the TaN resistors is an S 11 network parameter associated with the first and second TaN resistors as a 2-port pair;

the S 11 network parameter is determined through selective connection of the first and second TaN resistors to a balun device coupled to a network analyzer, the balun device and network analyzer included within an external testing device with respect to a chip on which the circuit under test is formed, and in combination with a variable current source included within the testing device, the variable current source configured to supply current individually through the first and second TaN resistors; and

wherein the variable current source is also configured to generate a level of current sufficient to correspond to the trimming voltage used to alter the resistance value of the first and second TaN resistors.

7. The method of claim 6 , wherein the testing device further comprises a double pole switch configured to couple one end of the first and second TaN resistors to the balun device in a first position, and to a pair of current mirror devices in a second position, the current mirror devices configured to generate corresponding trimming voltages across the first and second TaN resistors.

8. The method of claim 2 , wherein the trimming voltage used for altering the resistance of the first and second TaN resistors exceeds a designed operational voltage thereacross.