System and method for testing pattern sensitive algorithms for semiconductor design
View Patent ↗A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
1. A method for generating test patterns for a pattern sensitive algorithm, comprising:
extracting feature samples from a layout design utilizing Walsh patterns and correlation with either Walsh patterns or low resolution Walsh transforms;
grouping the extracted feature samples into clusters;
selecting at least one area from the layout design that covers a feature sample from each cluster; and
saving each pattern layout covered by the at least one area as a test pattern.
2. The method of claim 1 , wherein the step of extracting feature samples is done by sampling regions on at least one layer of the layout design.
3. The method of claim 1 , wherein the extracted feature samples are saved as feature vectors.
4. The method of claim 1 , wherein there are no empty clusters.
5. The method of claim 1 , wherein an overlap between the clusters is minimized using a technique selected from a group consisting of modifying an objective function, penalizing overlap and merging the clusters with substantial overlap.
6. The method of claim 1 , wherein the at least one area comprises at least one rectangle.
7. The method of claim 1 , wherein each cluster has a cluster mean and each feature sample within a cluster resides within a distance epsilon from the cluster mean.
8. The method of claim 1 , further comprising a step of testing pattern sensitive algorithm with a set of test patterns.
9. A method for processing patterns having been identified as creating flaws in a pattern sensitive algorithm, comprising:
sampling patterns associated with flaws into a plurality of sampled patterns;
grouping the plurality of sampled patterns into clusters such that location information and flaw severity are maintained; and
sorting the plurality of sampled patterns by the flaw severity and cluster membership.
10. A method for generating test patterns for a pattern sensitive algorithm, comprising:
extracting feature samples from a layout design;
grouping the extracted feature samples into clusters utilizing an algorithm that includes a penalized objective function;
selecting at least one area from the layout design that covers a feature sample from each cluster; and
saving each pattern layout covered by the at least one area as a test pattern.