Fast/slow state machine latch
View Patent ↗A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a delayed output, a second latch with an undelayed output, an inverter for coupling the delayed output of the first latch to an input of the second latch, and an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch. A method for incorporating low power multiplexer circuits into a circuit design with minimal input from a circuit designer is also provided.
1. A state machine latch having a dual output to drive a select line of a multiplexer in an integrated circuit, comprising:
a first latch with a delayed output;
a second latch with an undelayed output;
an inverter for coupling the delayed output of the first latch to an input of the second latch; and
an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch.
2. The state machine latch of claim 1 , wherein the delayed output comprises a slow select signal and wherein the undelayed output comprises a fast select signal.
3. The state machine latch of claim 2 , wherein the fast select signal comprises an inverse of a previous slow select signal provided by the first latch.
4. The state machine latch of claim 2 , wherein the slow select signal comprises an exclusive-OR of the data input and a previous slow select signal provided by the first latch.
5. The state machine latch of claim 2 , wherein the multiplexer comprises a single toggle, low power multiplexer.
6. The state machine latch of claim 5 , wherein the fast select signal is timed to arrive at the select line of the multiplexer before a fastest data arrives at a data-in port of the multiplexer, and wherein the slow select signal is timed to arrive at the select line of the multiplexer after a slowest data arrives at the data-in port of the multiplexer.
7. The state machine latch of claim 6 , further comprising:
a delay circuit coupled between the delayed output of the first latch and the select line of the multiplexer to ensure a proper timing of the slow select signal.
8. An integrated circuit, comprising:
a low power multiplexer circuit; and
a state machine latch for driving a select line of the low power multiplexer circuit, the state machine latch comprising:
a first latch with a delayed output;
a second latch with an undelayed output;
an inverter for coupling the delayed output of the first latch to an input of the second latch; and
an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch.
9. The integrated circuit of claim 8 , wherein the delayed output comprises a slow select signal and wherein the undelayed output comprises a fast select signal.
10. The integrated circuit of claim 9 , wherein the fast select signal comprises an inverse of a previous slow select signal provided by the first latch.
11. The integrated circuit of claim 9 , wherein the slow select signal comprises an exclusive-OR of the data input and a previous slow select signal provided by the first latch.
12. The integrated circuit of claim 9 , wherein the low power multiplexer circuit comprises a single toggle, low power multiplexer circuit.
13. The integrated circuit of claim 12 , wherein the fast select signal is timed to arrive at the select line of the multiplexer before a fastest data arrives at a data-in port of the multiplexer, and wherein the slow select signal is timed to arrive at the select line of the multiplexer after a slowest data arrives at the data-in port of the multiplexer.
14. The integrated circuit of claim 13 , further comprising:
a delay circuit coupled between the delayed output of the first latch and the select line of the multiplexer to ensure a proper timing of the slow select signal.