Circuit and method to measure threshold voltage distributions in SRAM devices
View Patent ↗A circuit for inline testing of memory devices which provides information on the variation of the threshold voltage. The circuit includes an array of ring oscillators with a series of inverters, which already exist in the memory device. A control logic systematically steps through all of the ring oscillators by enabling each inverter and toggling the input. The mean frequency and its distribution is measured and recorded in an output circuit. The threshold voltage variation in the memory device is deduced from the ring oscillators. The circuit additionally includes two inverters place external of the memory device. Each ring oscillator is coupled to an inverter. The inverter preconditions the elements of the ring oscillator to prevent a resistive divider between the two transistors.
1. A circuit to measure characteristics of a memory device having a plurality of inverters with transistors of a first transistor type, the circuit comprising:
an array of ring oscillators, wherein each of said ring oscillators in said array (a) produces a ring oscillator output signal such that said array produces a plurality of ring oscillator output signals and (b) includes a plurality of inverters having transistors of said first transistor type;
a multiplexer connected to said array of ring oscillators to receive said plurality of ring oscillator output signals and to provide as an output, in response to a select signal, one of said plurality of ring oscillator output signals;
a control logic unit coupled to said array of ring oscillators and to said multiplexer, said control logic unit enabling each of said ring oscillators in said array so as to cause said array produce said plurality of ring oscillator output signals, further wherein said control logic unit provides said select signal; and
an output circuit receiving said plurality of ring oscillator output signals from said multiplexer;
wherein said output circuit measures output frequency variability in each of said plurality of ring oscillator output signals.
2. A circuit of claim 1 , wherein said memory device comprising a static random access memory device sizes and environment.
3. A circuit of claim 1 , wherein said ring inverters comprising n-channel field effect transistors.
4. A circuit of claim 1 , wherein said ring inverters comprising p-channel field effect transistors.
5. A circuit of claim 1 , further comprising at least two feedback inverters;
wherein said ring inverters divided into at least two groups, at least one feedback inverter coupled to associated said group of ring inverters.
6. A circuit of claim 5 , further wherein said groups include an equal number of inverters.
7. A circuit of claim 5 , further wherein said at least two feedback inverters are located external of the memory device.
8. A memory device comprising an array of ring oscillators received in the memory device;
wherein each of said array of ring oscillators includes a plurality of inverters formed from existing same-type devices of the memory device.
9. A memory device of claim 8 , further comprising a static random access memory device.
10. A memory device of claim 8 , wherein said ring inverters comprising n-channel field effect transistors.
11. A memory device of claim 8 , wherein said ring inverters comprising p-channel field effect transistors.
12. A memory device of claim 8 further comprising at least two feedback inverters;
wherein said ring inverters divided into at least two groups of ring inverters, each said feedback inverter coupled to associated said group of ring inverters.
13. A memory device of claim 12 wherein said groups of ring inverters include an equal number of inverters.
14. A memory device of claim 12 wherein said at least two feedback inverters are located external of the memory device.
15. A method of measuring threshold voltage distribution in a memory device, the method comprising the steps of:
providing an array of ring oscillators in the memory device, each ring oscillator including a plurality of ring inverters coupled in series;
wherein said plurality of ring inverters includes existing same type devices of the memory device.
16. A method of claim 15 further comprising the steps of:
grouping said plurality of ring inverters into at least two groups;
providing at least two feedback inverters for the groups of ring inverters; and
placing the at least two feedback inverters outside of the memory device.
17. A method of claim 16 further comprising the steps of:
enabling one or more ring oscillators of the array of ring oscillators;
toggling a first group of ring inverters of the array of ring oscillators;
toggling a first feedback inverter associated with the first group of ring inverters;
preconditioning the associated first group of ring inverters by the first feedback inverter;
toggling a subsequent group of ring inverters of the array of ring oscillators;
toggling an associated feedback inverters associated with the subsequent group of ring inverters;
preconditioning the associated subsequent group of ring inverters by the associated feedback inverter; and
repeating the toggling and preconditioning processes until all groups of ring inverters and all feedback inverters have been toggled and preconditioned.
18. A method of claim 17 further comprising the steps of:
sending a plurality of ring oscillator output signals to an output circuit;
storing the plurality of ring oscillator output signals in the output circuit; and
measuring an output frequency variation and frequency distribution of the plurality of ring oscillator output signals.
19. A method of claim 18 further comprising the step of determining the physical location of each ring inverter of the array of ring oscillators.