IP Library Granted Patent US 7,332,447
Granted Patent B2
US 7,332,447 · App. 11/164,481 · Granted Feb 19, 2008

Method of forming a contact

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,332,447
App. No.
11/164,481
Granted
Feb 19, 2008
Kind
B2
Abstract

A method of forming a contact is provided. A substrate having at least two metal oxide semiconductor devices is provided and a gap is formed between the two devices. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate. The first stress layer is formed by first forming a first stress material layer over the substrate to cover the metal-oxide semiconductor devices and to fill the gap, wherein the stress material inside the gap has a seam. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.

Claims (19)

1. A fabrication method of a contact, the method comprising:

providing a substrate having at least two metal oxide semiconductor devices already formed thereon, wherein the two metal oxide semiconductor devices comprise a gap therebetween;

forming a first stress layer over the substrate to cover the two metal oxide semiconductors, wherein the first stress layer is formed by:

forming a stress material layer over the substrate to cover the two metal oxide semiconductor devices and to fill the gap, wherein the stress material layer inside the gap comprises a seam; and

performing an etching process to remove a portion of the stress material layer inside the gap to expand a width of the seam;

forming a second stress layer on the first stress layer;

forming a dielectric layer on the second stress layer;

removing a portion of the dielectric layer, a portion of the first stress layer and a portion of the second stress layer inside the gap to expose a portion of a surface of the substrate to form a contact opening; and

filling a conductive layer in the contact opening.

2. The method of claim 1 , wherein before the step of forming the second stress layer, the step of forming the first stress layer is repeated for at least one time.

3. The method of claim 1 , wherein a material of the stress material layer comprises silicon nitride.

4. The method of claim 1 , wherein the step in fanning the stress material layer comprises performing plasma enhanced chemical vapor deposition.

5. The method of claim 1 , wherein a material of the second stress layer comprises silicon nitride.

6. The method of claim 1 , wherein the step in fanning the second stress material comprises performing plasma enhanced chemical vapor deposition.

7. The method of claim 1 , wherein a total stress of the first stress layer and the second stress layer is about 1 to 50 Gpa.

8. The method of claim 1 , wherein a total stress of the first stress layer and the second stress layer is about 1 to 10 GPa.

9. The method of claim 1 , wherein a total thickness of the first stress layer and the second stress layer is about 150 to 1500 angstroms.

10. The method of claim 1 , wherein the etching back process includes a dry etching process or a wet etching process.

11. The method of claim 1 , wherein a material in constituting the dielectric layer is selected from the group consisting of silicon oxide, phosphorous silicon glass, boron silicon glass, boron phosphorous silicon glass and undoped silicon glass/phosphorous silicon glass.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 24, 2005
From: CHEN, NENG-KUO; TSAI, TENG-CHUN; HUANG, CHIEN-CHUNG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 016812/0818 →