Low cost bonding pad and method of fabricating same
View Patent ↗A structure and a method of forming the structure. The structure including: an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene, dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric levels, a top surface of a last damascene or dual-damascene wire of the last wiring level substantially coplanar with a top surface of a corresponding last interlevel dielectric level; a capping layer in direct physical and electrical contact with a top surface of the last damascene or dual-damascene wire, the last damascene or dual-damascene wire comprising copper; a dielectric passivation layer formed on a top surface of the last interlevel dielectric level; and an aluminum pad in direct physical and electrical contact with the capping layer, a top surface of the aluminum pad not covered by the dielectric passivation layer.
1. A structure, comprising:
an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene or dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric levels, a top surface of a last damascene or dual-damascene wire of said last wiring level substantially coplanar with a top surface of a corresponding last interlevel dielectric level;
a capping layer in physical and electrical contact with a top surface of said last damascene or dual-damascene wire, said last damascene or dual-damascene wire comprising copper;
a dielectric passivation layer formed on a top surface of said last interlevel dielectric level; and
an aluminum pad having a bottom surface, a top surface and sidewalls connecting said top and bottom surfaces, said bottom surface of said aluminum pad in physical and electrical contact with said capping layer, said top surface of said aluminum pad coplanar with a top surface of said dielectric passivation layer, said dielectric passivation layer in direct contact with said sidewalls of said aluminum pad.
2. The structure of claim 1 , further including:
a ball or wire bond formed on a top surface of said aluminum pad.
3. The structure of claim 1 , further including:
a polyimide layer formed on a top surface of said aluminum pad and a top surface of said dielectric layer;
a terminal via formed in said polyimide layer, said top surface of said aluminum pad exposed in a bottom of said terminal via;
a ball limiting metallurgy layer in direct physical and electrical contact with said top surface of said aluminum pad; and
a solder ball in direct physical and electrical contact with a top surface of said ball limiting metallurgy layer.
4. The structure of claim 1 , wherein there is no passivation layer in direct contact with said top surface of said aluminum pad and there is no passivation layer between said aluminum pad and said last damascene or dual-damascene wire.
5. The structure of claim 1 , wherein said capping layer covers the entire top surface of said last damascene or dual-damascene wire.
6. The structure of claim 1 , wherein a perimeter of said last damascene or dual-damascene wire is located entirely within a perimeter of said capping layer.
7. The structure of claim 1 , wherein a perimeter of said aluminum pad is located entirely within a perimeter of said capping layer.
8. The structure of claim 1 , wherein said capping layer comprises CoWP.
9. The structure of claim 1 , wherein said capping layer comprises NiP, CoP, NiCoP, or NiWP.
10. A method, comprising:
forming an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene or dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric levels, a top surface of a last damascene or dual-damascene wire of said last wiring level substantially coplanar with a top surface of a corresponding last interlevel dielectric level;
forming a capping layer in direct physical and electrical contact with a top surface of said last damascene or dual-damascene wire, said last damascene or dual-damascene wire comprising copper;
forming a dielectric passivation layer formed on a top surface of said last interlevel dielectric level; and
forming an aluminum pad having a bottom surface, a top surface and sidewalls connecting said top and bottom surfaces, said bottom surface of said aluminum pad in physical and electrical contact with said capping layer, said top surface of said aluminum pad coplanar with a top surface of said dielectric passivation layer, said dielectric passivation layer in direct contact with said sidewalls of said aluminum pad.
11. The method of claim 10 , further including:
forming a ball or wire bond formed on a top surface of said aluminum pad.
12. The method of claim 10 , further including:
forming a polyimide layer formed on a top surface of said aluminum pad and a top surface of said dielectric layer;
forming a terminal via formed in said polyimide layer, said top surface of said aluminum pad exposed in a bottom of said terminal via;
forming a ball limiting metallurgy layer in direct physical and electrical contact with said top surface of said aluminum pad; and
forming a solder ball in direct physical and electrical contact with a top surface of said ball limiting metallurgy layer.
13. The method of claim 10 , wherein there is no passivation layer in direct contact with said top surface of said aluminum pad and there is no passivation layer between said aluminum pad and said last damascene or dual-damascene wire.
14. The method of claim 10 , wherein said capping layer covers the entire top surface of said last damascene or dual-damascene wire.
15. The method of claim 10 , wherein a perimeter of said last damascene or dual-damascene wire is located entirely within a perimeter of said capping layer.
16. The method of claim 10 , wherein a perimeter of said aluminum pad is located entirely within a perimeter of said capping layer.
17. The method of claim 10 , wherein said capping layer comprises CoWP.
18. The method of claim 10 , wherein said capping layer comprises NiP, CoP, NiCoP, or NiWP.
19. The method of claim 10 , wherein said capping layer is formed by electroless plating.
20. The method of claim 10 , wherein said aluminum pad is formed prior to formation of said passivation layer, said passivation layer covering said aluminum pad and further including performing a chemical-mechanical polish of said passivation layer, said chemical-mechanical polish of said passivation layer exposing said top surface of said aluminum pad.
21. The structure of claim 1 , wherein said dielectric passivation layer comprises a first dielectric layer on top of a second dielectric layer, a ring of said first dielectric layer immediately adjacent to said aluminum boding pad coplanar with said top surface of said dielectric passivation layer, said second dielectric layer not contacting said aluminum bonding pad.
22. The structure of claim 1 , wherein said damascene wire or said dual-damascene wire of said last wiring level further comprises a conductive liner formed on sidewalls and a bottom surface of said damascene wire or said dual-damascene wire of said last wiring level.
23. The method of claim 10 , wherein said dielectric passivation layer comprises a first dielectric layer on top of a second dielectric layer, a ring of said first dielectric layer immediately adjacent to said aluminum boding pad coplanar with said top surface of said dielectric passivation layer, said second dielectric layer not contacting said aluminum bonding pad.
24. The method of claim 10 , wherein said damascene wire or said dual-damascene wire of said last wiring level further comprises a conductive liner formed on sidewalls and a bottom surface of said damascene wire or said dual-damascene wire of said last wiring level.