Multi-mode integrated circuit structure
View Patent ↗A multi-mode integrated circuit structure. In one embodiment, an integrated circuit structure includes a first die having at least one first component disposed on a face, the first die fabricated using a first process that is optimal for operating the component in an first mode and a second die stacked on the first die, the second die having at least one second component disposed on a face and the second die fabricated using a second process separate from the first process that is optimal for operating the second component in a second mode. As such, the integrated circuit structure provides an electronic device with a single integrated circuit structure for performing operations optimally in more than one mode, such as operations in enhancement mode and operations in depletion mode.
1. A method of fabricating a unitary gallium arsenide monolithic microwave integrated circuit (MMIC) structure capable of operating in an enhancement/depletion (E/D) mode, comprising:
fabricating a first electronic component on a first die comprising gallium arsenide using a first fabrication process optimal for operating the first electronic component in an enhancement mode;
fabricating a second electronic component on a second die comprising gallium arsenide using a second fabrication process different from the first process, the second process being optimal for operating the second component in a depletion mode;
forming an electrically isolating interconnect layer, and
adjoining the first die to the second die to form the integrated circuit structure, wherein the electrically isolating interconnect layer is disposed between the first die and the second die, the interconnect layer being configured to electrically interconnect portions of the first and second dice.
2. The method of claim 1 , wherein the first die and the second die are stacked such that the combined height comprises a wafer-level height.
3. The method of claim 1 wherein the interconnect layer comprises electrically non-conductive interconnect spacers that provide electrical isolation between the first die and the second die.
4. The method of claim 1 wherein the adjoining further comprises adjoining the first die to the second in a face-to-face configuration.
5. The method of claim 1 wherein the adjoining further comprises adjoining the first die to the second in a configuration such that the face of the first die faces the same direction as the face of the second die.