IP Library Granted Patent US 8,218,042
Granted Patent B2
US 8,218,042 · App. 11/167,855 · Granted Jul 10, 2012

Solid-state image-sensing device and camera provided therewith

Assignee: Konica Minolta Holdings, Inc.
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Quick Facts
Patent No.
US 8,218,042
App. No.
11/167,855
Granted
Jul 10, 2012
Kind
B2
Abstract

By feeding an appropriate voltage as a signal φTX to a transfer gate TG, a MOS transistor T 1 , is operated in a threshold region. A potential linearly or natural logarithmically converted by a buried photodiode PD is transferred to an N-type floating diffusion layer FD so as to be fed out, as an image signal, via MOS transistors T 3 and T 4.

Claims (55)

1. A method of operating a solid-state image-sensing device comprising a plurality of pixels, wherein each pixel comprises:

a buried photodiode (PD) formed on a substrate and adapted to generate a photoelectric charge commensurate with an amount of incident light, the buried photodiode (PD) adapted to accumulate therewithin the resulting photoelectric charge;

a first transistor (T 1 ) having a transfer gate (TG) electrically connected to the buried photodiode (PD) and positioned on the substrate immediately adjacent the buried photodiode (PD), the transfer gate (TG) adapted to transfer the accumulated photoelectric charge from the buried photodiode, the transfer gate (TG) having a first electrode electrically connected to a source of a first electrical signal (φTX), the first transistor (T 1 ) having a floating diffusion layer (FD) electrically connected to the transfer gate (TG) and positioned on the substrate immediately adjacent the transfer gate (TG), the floating diffusion layer (FD) having a second electrode and adapted to accumulate therewithin the photoelectric charge transferred by the transfer gate (TG), the first transistor (T 1 ) having the buried photodiode corresponding to a third electrode thereof;

a second transistor (T 2 ) having a first electrode electrically connected to the second electrode of the first transistor (T 1 ), a second electrode connected to a first direct-current voltage (VPD), and a gate electrically connected to a second electrical signal (φRS);

a third transistor (T 3 ) having a gate electrically connected to the second electrode of the first transistor (T 1 ), a first electrode connected to the direct-current voltage (VPD), and a second electrode; and

a fourth transistor (T 4 ) having a first electrode electrically connected to second electrode of the third transistor (T 3 ), a gate electrically connected to a third electrical signal (φV), and second electrode electrically connected to an output signal line,

the method comprising the following steps in sequence:

setting the third electrical signal (φV) to a low voltage sufficient to turn off the fourth transistor (T 4 );

setting the first electrical signal (φTX) to a medium voltage level and setting the second electrical signal (φRS) to a high voltage, the first electrical signal (φTX) and the second electrical signal (φRS) being sufficient to make a potential at the transfer gate (TG) lower than a potential at the buried photodiode (PD) and to make a potential at the floating diffusion layer (FD) nearly equal to a potential of the direct-current voltage (VPD);

setting the third electrical signal (φV) to a pulse of high voltage, the high voltage of the third electrical signal (φV) being greater than the low voltage of the third electrical signal (φV) and being sufficient to turn on the fourth transistor (T 4 );

setting the third electrical signal (φV) to the low voltage of the third electrical signal (φV);

setting the second electrical signal (φRS) to a low voltage, the low voltage being less than the high voltage of the second electrical signal (φRS), and being sufficient to turn off the second transistor (T 2 ) and to bring the potential of the floating diffusion layer (FD) into a floating state;

setting the first electrical signal (φTX) to a high voltage level sufficient to cause the buried photodiode (PD) to transfer accumulated potential therein to the floating diffusion layer (FD), the high voltage level of the first electrical signal (φTX) being greater than the medium voltage level of the first electrical signal (φTX);

setting the first electrical signal (φTX) to a low voltage level lower than the medium voltage level of the first electrical signal (φTX) and being sufficient to inhibit transfer of accumulated potential by the buried photodiode (PD) to the floating diffusion layer (FD);

setting the third electrical signal (φV) to a pulse of the high voltage of the third electrical signal (φV) ;

setting the third electrical signal (φV) to the low voltage of the third electrical signal (φV);

setting the first electrical signal (φTX) to the medium voltage level of the first electrical signal (φTX); and

setting the second electrical signal (φRS) to the high voltage of the second electrical signal (φRS) to turn on the second transistor (T 2 ).

2. A method of operating a solid-state image-sensing device comprising a plurality of pixels, wherein each pixel comprises:

a buried photodiode (PD) formed on a substrate and adapted to generate a photoelectric charge commensurate with an amount of incident light, the buried photodiode (PD) adapted to accumulate therewithin the resulting photoelectric charge;

a first transistor (T 1 ) having a transfer gate (TG) electrically connected to the buried photodiode (PD) and positioned on the substrate immediately adjacent the buried photodiode (PD), the transfer gate (TG) adapted to transfer the accumulated photoelectric charge from the buried photodiode, the transfer gate (TG) having a first electrode electrically connected to a source of a first electrical signal (φTX), the first transistor (T 1 ) having a floating diffusion layer (FD) electrically connected to the transfer gate (TG) and positioned on the substrate immediately adjacent the transfer gate (TG), the floating diffusion layer (FD) having a second electrode and adapted to accumulate therewithin the photoelectric charge transferred by the transfer gate (TG), the first transistor (T 1 ) having the buried photodiode corresponding to a third electrode thereof;

a second transistor (T 2 ) having a first electrode electrically connected to the second electrode of the first transistor (T 1 ), a second electrode connected to a first direct-current voltage (VPD), and a gate electrically connected to a second electrical signal (φRS);

a third transistor (T 3 ) having a gate electrically connected to the second electrode of the first transistor (T 1 ), a first electrode connected to the direct-current voltage (VPD), and a second electrode; and

a fourth transistor (T 4 ) having a first electrode electrically connected to second electrode of the third transistor (T 3 ), a gate electrically connected to a third electrical signal (φV), and second electrode electrically connected to an output signal line,

the method comprising the following steps in sequence:

setting the first electrical signal (φTX) to a low voltage level and setting the second electrical signal (φRS) to a low voltage, the first electrical signal (φTX) and the second electrical signal (φRS) being sufficient to turn off the first transistor (T 1 ) and the second transistor (T 2 );

setting the second electrical signal (φRS) to a high voltage, the high voltage being greater than the low voltage of the second electrical signal (φRS) and being sufficient to turn on the second transistor (T 2 );

setting the first electrical signal (φTX) to a high voltage level to raise a potential at the transfer gate (TG), the high voltage level of the first electrical signal (φTX) being greater than the low voltage of the first electrical signal (φTX);

setting the first electrical signal (φTX) to a medium voltage level; the medium voltage level being between the high and low voltage levels of the first electrical signal (φTX) and being sufficient to cause the buried photodiode (PD) to start exposure;

setting the second electrical signal (φRS) to the low voltage of the second electrical signal (φRS) so as to turn off the second transistor (T 2 );

setting the first electrical signal (φTX) to the high voltage level of the first electrical signal (φTX); and

setting the first electrical signal (φTX) to the low voltage level of the first electrical signal (φTX).

3. The method of operating a solid-state image-sensing device of claim 2 , further comprising the following subsequent steps in sequence:

setting the third electrical signal (φV) to a pulse of high voltage;

setting the second electrical signal (φRS) to the high voltage of the second electrical signal (φRS);

setting the second electrical signal (φRS) to the low voltage of the second electrical signal (φRS); and

setting the third electrical signal (φV) to a pulse of high voltage.

4. A method of operating a solid-state image-sensing device comprising a plurality of pixels, wherein each pixel comprises:

a buried photodiode (PD) formed on a substrate and adapted to generate a photoelectric charge commensurate with an amount of incident light, the buried photodiode (PD) adapted to accumulate therewithin the resulting photoelectric charge;

a first transistor (T 1 ) having a transfer gate (TG) electrically connected to the buried photodiode (PD) and positioned on the substrate immediately adjacent the buried photodiode (PD), the transfer gate (TG) adapted to transfer the accumulated photoelectric charge from the buried photodiode, the transfer gate (TG) having a first electrode electrically connected to a source of a first electrical signal (φTX), the first transistor (T 1 ) having a floating diffusion layer (FD) electrically connected to the transfer gate (TG) and positioned on the substrate immediately adjacent the transfer gate (TG), the floating diffusion layer (FD) having a second electrode and adapted to accumulate therewithin the photoelectric charge transferred by the transfer gate (TG), the first transistor (T 1 ) having the buried photodiode corresponding to a third electrode thereof;

a second transistor (T 2 ) having a first electrode electrically connected to the second electrode of the first transistor (T 1 ), a second electrode connected to a first direct-current voltage (VPD), and a gate electrically connected to a second electrical signal (φRS);

a third transistor (T 3 ) having a gate electrically connected to the second electrode of the first transistor (T 1 ), a first electrode connected to the direct-current voltage (VPD), and a second electrode; and

a fourth transistor (T 4 ) having a first electrode electrically connected to second electrode of the third transistor (T 3 ), a gate electrically connected to a third electrical signal (φV), and second electrode electrically connected to an output signal line,

the method comprising the following steps in sequence:

setting the first electrical signal (φTX) to a low voltage level and setting the second electrical signal (φRS) to a low voltage, the first electrical signal (φTX) and the second electrical signal (φRS) being sufficient to turn off the first transistor (T 1 ) and the second transistor (T 2 );

setting the second electrical signal (φRS) to a high voltage, the high voltage being greater than the low voltage of the second electrical signal (φRS);

setting the first electrical signal (φTX) to a high voltage level to raise a potential at the transfer gate (TG), the high voltage level of the first electrical signal (φTX) being greater than the low voltage of the first electrical signal (φTX);

setting the first electrical signal (φTX) to a medium voltage level; the medium voltage level being between the high and low voltage levels of the first electrical signal (φTX) and being sufficient to cause the buried photodiode (PD) to start exposure; and

setting the first electrical signal (φTX) to the low voltage level of the first electrical signal (φTX).

5. The method of operating a solid-state image-sensing device of claim 4 , further comprising the following subsequent steps in sequence:

setting the third electrical signal (φV) to a pulse of high voltage;

setting the second electrical signal (φRS) to the low voltage of the second electrical signal (φRS);

setting the first electrical signal (φTX) to the high voltage level of the first electrical signal (φTX);

setting the first electrical signal (φTX) to the low voltage level of the first electrical signal (φTX); and

setting the third electrical signal (φV) to a pulse of high voltage.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2016
From: KONICA MINOLTA, INC.
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040182/0404 →
MERGER AND CHANGE OF NAME Recorded Aug 18, 2016
From: KONICA MINOLTA ADVANCED LAYERS, INC.; KONICA MINOLTA HOLDINGS, INC.; KONICA MINOLTA HOLDINGS, INC.
To: KONICA MINOLTA, INC.
Reel/Frame 039785/0733 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2005
From: MIYATAKE, SHIGEHIRO; KAKUMOTO, TOMOKAZU
To: KONICA MINOLTA HOLDINGS, INC.
Reel/Frame 016746/0235 →
Priority Claims (2)
JP 2004-198114 · Jul 5, 2004 · national
JP 2005-100432 · Mar 31, 2005 · national
Continuity (1)
Related Publication 20060001061A1 · Jan 5, 2006