System and method for examining high-frequency clock-masking signal patterns at full speed
View Patent ↗The present invention provides for a method for examining high-frequency clock-masking signal patterns at a reduced frequency. A first mode of a first shift register is selected. A plurality of bits is loaded on the first shift register at a first frequency. A second mode of the first shift register is selected. A first mode of a second shift register is selected. The plurality of bits is loaded on the second shift register. A second mode of the second shift register is selected. A first mode of a third shift register is selected. The plurality of bits is loaded on the third shift register. A second mode of the third shift register is selected and the plurality of bits is loaded from the third shift register at a second frequency, where the second frequency is lower than the first frequency, thereby providing for examining high-frequency clock-masking signal patterns at a reduced frequency.
1. A method for examining high-frequency clock-masking signal patterns at a reduced frequency, comprising:
selecting a first mode of a first shift register;
loading a plurality of bits on the first shift register at a first frequency;
selecting a second mode of the first shift register;
selecting a first mode of a second shift register;
loading the plurality of bits on the second shift register;
selecting a second mode of the second shift register;
selecting a first mode of a third shift register;
loading the plurality of bits on the third shift register;
selecting a second mode of the third shift register; and
loading the plurality of bits from the third shift register at a second frequency, where the second frequency is lower than the first frequency, thereby providing for examining high-frequency clock-masking signal patterns at a reduced frequency.
2. The method as recited in claim 1 , further comprising testing the plurality of bits loaded from the third shift register.
3. The method as recited in claim 1 , wherein selecting a first mode of the second shift register comprises setting a serial disable bit to a logic low.
4. The method as recited in claim 1 , wherein selecting a second mode of the second shift register comprises setting a serial disable bit to a logic high.
5. The method as recited in claim 1 , wherein the first shift register comprises a serial/parallel shift register and the third shift register comprises a serial/parallel shift register.
6. The method as recited in claim 1 , wherein the first mode of the first shift register comprises a parallel mode and the second mode of the first shift register comprises a serial mode.
7. The method as recited in claim 1 , wherein the first mode of the third shift register comprises a parallel mode and the second mode of the third shift register comprises a serial mode.
8. The method as recited in claim 1 , wherein loading a plurality of bits on the first shift register further comprises receiving a clock signal and loading the plurality of bits in response to the received clock signal.
9. The method as recited in claim 8 , wherein the clock signal is a high frequency clock signal.
10. The method as recited in claim 1 , wherein loading a plurality of bits on the third shift register further comprises receiving a clock signal and loading the plurality of bits in response to the received clock signal.
11. The method as recited in claim 1 , wherein:
selecting a first mode of a first shift register is performed by a first serial/parallel shift register;
loading a plurality of bits on the first shift register at a first frequency is performed by the first serial/parallel shift register;
selecting a second mode of the first shift register is performed by the first serial/parallel shift register;
selecting a first mode of a second shift register is performed by a first shift register;
loading the plurality of bits on the second shift register is performed by the first shift register;
selecting a second mode of the second shift register is performed by the first shift register;
selecting a first mode of a third shift register is performed by a second serial/parallel shift register;
loading the plurality of bits on the third shift register is performed by the second serial/parallel shift register;
selecting a second mode of the third shift register is performed by the second serial/parallel shift register; and
loading the plurality of bits from the third shift register at a second frequency, where the second frequency is lower than the first frequency, is performed by the second serial/parallel shift register.
12. A system, comprising:
a first shift register configured to receive a high frequency clock signal, a first mode select signal, and a plurality of bits;
the first shift register further configured to load the plurality of bits in a parallel mode or to operate in a serial mode, in response to the first mode select signal;
a second shift register coupled to the first shift register and configured to receive the high frequency clock signal and a serial disable signal, and to receive the plurality of bits from the first shift register, in response to the serial disable signal;
a third shift register coupled to the second shift register and configured to receive a low frequency clock signal and a second mode select signal, and to receive the plurality of bits from the second shift register; and
the third shift register further configured to load the plurality of bits in a parallel mode, in response to the second mode select signal, and to operate in a serial mode, in response to the second mode select signal.
13. The system as recited in claim 12 , wherein the first shift register is a serial/parallel shift register and the third shift register is a serial/parallel shift register.
14. The system as recited in claim 12 , wherein the high frequency clock is configured at a frequency of at least one gigaHertz.
15. The system as recited in claim 12 , wherein the high frequency clock is configured at a frequency of at least five gigaHertz.
16. The system as recited in claim 12 , further comprising a test circuit coupled to the third shift register and configured to receive the plurality of bits from the third shift register in a serial mode.
17. The system as recited in claim 12 , wherein the first shift register further comprises a parallel/serial select pin configured to receive the first mode select signal.
18. The system as recited in claim 12 , wherein the third shift register further comprises a parallel/serial select pin configured to receive the second mode select signal.
19. The system as recited in claim 12 , wherein the second shift register further comprises a serial disable pin configured to receive the serial disable signal.
20. A processor for examining high-frequency clock-masking signal patterns at a reduced frequency, the processor including a computer program, comprising:
computer program code for selecting a first mode of a first shift register;
computer program code for loading a plurality of bits on the first shift register at a first frequency;
computer program code for selecting a second mode of the first shift register;
computer program code for selecting a first mode of a second shift register;
computer program code for loading the plurality of bits on the second shift register
computer program code for selecting a second mode of the second shift register;
computer program code for selecting a first mode of a third shift register;
computer program code for loading the plurality of bits on the third shift register;
computer program code for selecting a second mode of the third shift register; and
computer program code for loading the plurality of bits from the third shift register at a second frequency, where the second frequency is lower than the first frequency, thereby providing for examining high-frequency clock-masking signal patterns at a reduced frequency.