IP Library Granted Patent US 7,288,456
Granted Patent B2
US 7,288,456 · App. 11/169,040 · Granted Oct 30, 2007

Semiconductor device and method for fabricating the same

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Quick Facts
Patent No.
US 7,288,456
App. No.
11/169,040
Granted
Oct 30, 2007
Kind
B2
Abstract

A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.

Claims (13)

1. A method for fabricating a semiconductor device, comprising the steps of:

forming a lower hydrogen-barrier film over a semiconductor substrate;

forming capacitor rows over the lower hydrogen-barrier film, the capacitor rows including a plurality of capacitors each having a capacitive insulating film made of a ferroelectric material or a high dielectric material;

forming an interlayer dielectric film covering the capacitor rows;

forming, in the interlayer dielectric film, an open trench exposing the lower hydrogen-barrier film where the lower hydrogen-barrier film is located outside the capacitor rows; and

forming an upper hydrogen-barrier film on the interlayer dielectric film so that the upper hydrogen-barrier film is in contact with the lower hydrogen-barrier film where the upper hydrogen-barrier film is on the bottom face of the open trench.

2. The method of claim 1 , wherein the step of forming the open trench in the interlayer dielectric film includes the step of forming a plurality of the open trenches in parallel with each other.

3. The method of claim 1 , wherein the open trench has a cross-sectional configuration that is tapered and flares upward.

4. The method of claim 1 , wherein in the lower-hydrogen-barrier-film formation step, the lower hydrogen-barrier film is formed directly on bit lines.

5. The method of claim 1 , wherein a lower electrode, the capacitive insulating film, and an upper electrode in each said capacitor have a cross section of a recess, and the lateral faces of each said recess are tapered and flare upward.

6. The method of claim 1 , wherein in the upper-hydrogen-barrier-film formation step, the upper hydrogen-barrier film is formed directly on upper electrodes.

7. The method of claim 1 , further comprising the step of forming interconnects directly on the upper hydrogen-barrier film, after the upper-hydrogen-barrier-film formation step is performed.

8. The method of claim 1 , wherein the capacitor-row formation step includes the step of connecting upper electrodes of the capacitors with each other so that the upper electrodes form a cell plate, and electrically connecting an upper electrode and a lower electrode in one capacitor connected to the cell plate, thereby making said one capacitor be a conducting dummy capacitor whose upper and lower electrodes are electrically connected with each other.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2020
From: PANNOVA SEMIC, LLC
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 053755/0859 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →