Method of fabricating semiconductor device
View Patent ↗An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region ( 3 ), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and′ a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12 , so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
1. A method of fabricating a semiconductor device, comprising steps of:
(a) forming a gate electrode of an n-channel MISFET over a main surface of a first semiconductor region of p-type conductivity formed in a semiconductor body and a gate electrode of a p-channel MISFET over a main surface of a second semiconductor region of n-type conductivity formed in said semiconductor body;
(b) after said step (a), implanting ions in said first semiconductor region to form a third semiconductor region of n-type conductivity;
(c) after said step (b), forming side wall spacers on side surfaces of said gate electrodes;
(d) after said step (c), implanting ions in said first semiconductor region to form a fourth semiconductor region of n-type conductivity;
(e) after said step (c), implanting ions in said first semiconductor region to form a fifth semiconductor region of n-type conductivity; and
(f) after said steps (d) and (e), forming a cobalt silicide layer in said fourth semiconductor region,
wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said fourth semiconductor region is greater than an impurity concentration of said fifth semiconductor region,
wherein a depth of said fifth semiconductor region is greater than a depth of said fourth semiconductor region,
wherein said gate electrode of said n-channel MISFET is an N-type gate electrode, and
wherein said gate electrode of said p-channel MISFET is P-type gate electrode.
2. A method of fabricating a semiconductor device according to claim 1 , wherein each of a gate length of said gate electrodes is less than 200 nm.
3. A method of fabricating a semiconductor device according to claim 1 , wherein said MISFETs are included in a static random access memory (SRAM).
4. A method of fabricating a semiconductor device according to claim 1 , wherein said MISFETs are included in a dynamic random access memory (DRAM).
5. A method of fabricating a semiconductor device according to claim 1 , wherein said MISFETs are included in a logic LSI.
6. A method of fabricating a semiconductor device according to claim 1 , wherein said MISFETs are included in a LSI having both memory and logic.
7. A method of fabricating a semiconductor device according to claim 1 , wherein said step (f) includes sub-steps of:
forming a cobalt film over said fourth semiconductor region;
forming a titanium nitride (TiN) film over said cobalt film; and
performing a heat treatment to form said cobalt silicide layer in said fourth semiconductor region.
8. A method of fabricating a semiconductor device according to claim 1 , wherein in said step (d), arsenic ion is implanted, and wherein in said step (e), phosphorus ion is implanted.
9. A method of fabricating a semiconductor device according to claim 1 , further comprising the step of:
(g) after said step (c), forming an insulating film over said third semiconductor region, wherein said steps (d) and (e) are conducted through said insulating film.
10. A method of fabricating a semiconductor device according to claim 1 , wherein a junction depth of said third semiconductor region is shallower than a junction depth of said fifth semiconductor region.
11. A method of fabricating a semiconductor device according to claim 1 , wherein said third semiconductor region serves as a lightly doped drain (LDD).
12. A method of fabricating a semiconductor device according to claim 1 , wherein said fourth semiconductor region and said fifth semiconductor region serve as source or drain regions.
13. A method of fabricating a semiconductor device, comprising steps of:
(a) forming a gate electrode of a n-channel MISFET over a main surface of a first semiconductor region of p-type conductivity formed in a semiconductor body and a gate electrode of a p-channel MISFET over a main surface of a second semiconductor region of n-type conductivity formed in said semiconductor body;
(b) after said step (a), implanting ions in said first semiconductor region to form a third semiconductor region of n-type conductivity;
(c) after said step (b), forming side wall spacers on side surfaces of said gate electrodes;
(d) after said step (c), implanting ions in a first region of said first semiconductor region to form a fourth semiconductor region of n-type conductivity;
(e) after said step (c), implanting ions in a second region, deeper than said first region, of said first semiconductor region to form a fifth semiconductor region of n-type conductivity; and
(f) after said steps (d) and (e), forming a cobalt silicide layer in said fourth semiconductor region,
wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said fourth semiconductor region is greater than an impurity concentration of said fifth semiconductor region,
wherein said gate electrode of said n-channel MISFET is an N-type gate electrode, and
wherein said gate electrode of said p-channel MISFET is a P-type gate electrode.
14. A method of fabricating a semiconductor device according to claim 13 , wherein a gate length of each of said gate electrodes is less than 200 nm.
15. A method of fabricating a semiconductor device according to claim 13 , wherein, in said step (d), arsenic ion is implanted, and wherein, in said step (e), phosphorus ion is implanted.
16. A method of fabricating a semiconductor device, comprising steps of:
(a) forming a gate electrode of a n-channel MISFET over a main surface of a first semiconductor region of p-type conductivity formed in a semiconductor body and a gate electrode of a p-channel MISFET over a main surface of a second semiconductor region of n-type conductivity formed in said semiconductor body, wherein each of said element forming regions is defined by a shallow groove isolation layer such that said shallow groove isolation layer is formed by a OMP method;
(b) after said step (a), implanting ions in said first semiconductor region to form a third semiconductor region of n-type conductivity;
(c) after said step (b), forming side wall spacers on side surfaces of said gate electrodes;
(d) after said step (c), implanting ions in a first region of said first semiconductor region to form a fourth semiconductor region of n-type conductivity;
(e) after said step (c), implanting ions in a second region, deeper than said first region, of said first semiconductor region to form a fifth semiconductor region of n-type conductivity; and
(f) after said steps (d) and (e), forming a cobalt suicide layer in said fourth semiconductor region,
wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said fourth semiconductor region is greater than an impurity concentration of said fifth semiconductor region,
wherein said gate electrode of said n-channel MISFET is a N-type gate electrode, and
wherein said gate electrode of said p-channel MISFET is a P-type gate electrode.
17. A method of fabricating a semiconductor device according to claim 16 , wherein a gate length of each of said gate electrodes is less than 200 nm.
18. A method of fabricating a semiconductor device according to claim 16 , wherein, in said step (d), arsenic ion is implanted, and wherein, in said step (e), phosphorus ion is implanted.