Method of fabricating semiconductor device
View Patent ↗An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region ( 3 ), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12 , so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
1. A method of fabricating a semiconductor device, comprising steps of:
(a) forming a gate electrode of a MISFET over a main surface of a first semiconductor region of a first conductivity type formed in a semiconductor body, wherein a gate length of said gate electrode is less than 200 nm, wherein an element forming region is defined by a shallow groove isolation layer such that said shallow groove isolation layer is formed by a CMP method;
(b) after said step (a), implanting ions in said first semiconductor region to form a second semiconductor region of a second conductivity type opposite to said first conductivity type;
(c) after said step (b), forming a side wall spacer on a side surface of said gate electrode;
(d) after said step (c), implanting ions in said first semiconductor region to form a third semiconductor region of said second conductivity type;
(e) after said step (c), implanting ions in said first semiconductor region to form a fourth semiconductor region of said second conductivity type; and
(f) after said steps (d) and (e), forming a cobalt silicide layer in said third semiconductor region,
wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said third semiconductor region is greater than an impurity concentration of said fourth semiconductor region, and
wherein a depth of said fourth semiconductor region is greater than a depth of said third semiconductor region.
2. A method of fabricating a semiconductor device according to claim 1 , wherein said MISFET is included in a static random access memory (SRAM).
3. A method of fabricating a semiconductor device according to claim 1 , wherein said MISFET is included in a dynamic random access memory (DRAM).
4. A method of fabricating a semiconductor device according to claim 1 , wherein said MISFET is included in a logic LSI.
5. A method of fabricating a semiconductor device according to claim 1 , wherein said MISFET is included in an LSI having both memory and logic.
6. A method of fabricating a semiconductor device according to claim 1 , wherein said step (f) includes sub-steps of:
forming a cobalt film over said third semiconductor region;
forming a titanium nitride (TiN) film over said cobalt film; and
performing a heat treatment to form said cobalt silicide layer in said third semiconductor region.
7. A method of fabricating a semiconductor device according to claim 1 , wherein in said step (d), arsenic ion is implanted, and wherein in said step (e), phosphorus ion is implanted.
8. A method of fabricating a semiconductor device according to claim 1 , wherein in said steps (d) and (e), boron ions are implanted.
9. A method of fabricating a semiconductor device according to claim 1 , further comprising the step of:
(g) after said step (c), forming an insulating film over said second semiconductor region, wherein said steps (d) and (e) are conducted through said insulating film.
10. A method of fabricating a semiconductor device according to claim 1 , wherein a junction depth of said second semiconductor region is shallower than a junction depth of said fourth semiconductor region.
11. A method of fabricating a semiconductor device according to claim 1 , wherein said second semiconductor region serves as a lightly doped drain (LDD).
12. A method of fabricating a semiconductor device according to claim 1 , wherein said third semiconductor region and said fourth semiconductor region serve as source or drain regions.
13. A method of fabricating a semiconductor device according to claim 1 , wherein, in said step (d), said ions are introduced in a first region in said first semiconductor region, and wherein, in said step (e), said ions are introduced in a second region deeper than said first region in said first semiconductor region.
14. A method of fabricating a semiconductor device, comprising steps of:
(a) forming a gate electrode of a MISFET over a main surface of a first semiconductor region of a first conductivity type formed in a semiconductor body, wherein a gate length of said gate electrode is less than 200 nm, and wherein an element forming region is defined by a shallow groove isolation layer such that said shallow groove isolation layer is formed by a CMP method;
(b) after said step (a), implanting ions in said first semiconductor region to form a second semiconductor region of a second conductivity type opposite to said first conductivity type;
(c) after said step (b), forming a side wall spacer on a side surface of said gate electrode;
(d) after said step (c), implanting ions in a first region in said first semiconductor region to form a third semiconductor region of said second conductivity type;
(e) after said step (c), implanting ions in a second region deeper than said first region in said first semiconductor region to form a fourth semiconductor region of said second conductivity type; and
(f) after said steps (d) and (e), forming a cobalt silicide layer in said third semiconductor region,
wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said third semiconductor region is greater than an impurity concentration of said fourth semiconductor region.
15. A method of fabricating a semiconductor device according to claim 14 , wherein said MISFET is included in a static random access memory (SRAM).
16. A method of fabricating a semiconductor device according to claim 14 , wherein said MISFET is included in a dynamic random access memory (DRAM).
17. A method of fabricating a semiconductor device according to claim 14 , wherein, in said step (d), arsenic ion is implanted, and wherein, in said step (e), phosphorus ion is implanted.
18. A method of fabricating a semiconductor device according to claim 14 , wherein, in said steps (d) and (e), boron ions are implanted.
19. A method of fabricating a semiconductor device, comprising steps of:
(a) forming a gate electrode of a MISFET over a main surface of a first semiconductor region of a first conductivity type formed in a semiconductor body, wherein a gate length of said gate electrode is less than 200 nm, and wherein an element forming region is defined by a shallow groove isolation layer such that said shallow groove isolation layer is formed by a CMP method;
(b) after said step (a), implanting ions in said first semiconductor region to form a second semiconductor region of a second conductivity type opposite to said first conductivity type;
(c) after said step (b), forming a side wall spacer on a side surface of said gate electrode;
(d) after said step (c), implanting ions in a first region in said first semiconductor region to form a third semiconductor region of said second conductivity type;
(e) after said step (c), implanting ions at a second position deeper than said first position in said first semiconductor region to form a fourth semiconductor region of said second conductivity type; and
(f) after said steps (d) and (e), forming a cobalt silicide layer in said third semiconductor region,
wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said third semiconductor region is greater than an impurity concentration of said fourth semiconductor region.
20. A method of fabricating a semiconductor device according to claim 19 , wherein said MISFET is included in a static random access memory (SRAM).
21. A method of fabricating a semiconductor device according to claim 19 , wherein said MISFET is included in a dynamic random access memory (DRAM).
22. A method of fabricating a semiconductor device according to claim 19 , wherein, in said step (d), arsenic ion is implanted, and wherein, in said step (e), phosphorus ion is implanted.
23. A method of fabricating a semiconductor device according to claim 19 , wherein, in said steps (d) and (e), boron ions are implanted.
24. A method of fabricating a semiconductor device, comprising steps of:
(a) forming a gate electrode of a MISFET over a main surface of a first semiconductor region of a first conductivity type formed in a semiconductor body, wherein an element forming region is defined by a shallow groove isolation layer such that said shallow groove isolation layer is formed by a CMP method;
(b) after said step (a), implanting ions in said first semiconductor region to form a second semiconductor region of a second conductivity type opposite to said first conductivity type;
(c) after said step (b), forming a side wall spacer on a side surface of said gate electrode;
(d) after said step (c), implanting ions in a first region in said first semiconductor region to form a third semiconductor region of said second conductivity type;
(e) after said step (c), implanting ions in a second region deeper than said first region in said first semiconductor region to form a fourth semiconductor region of said second conductivity type; and
(f) after said steps (d) and (e), forming a cobalt silicide layer in said third semiconductor region,
wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said third semiconductor region is greater than an impurity concentration of said fourth semiconductor region.
25. A method of fabricating a semiconductor device according to claim 24 , wherein said MISFET is included in a static random access memory (SRAM).
26. A method of fabricating a semiconductor device according to claim 24 , wherein said MISFET is included in a dynamic random access memory (DRAM).
27. A method of fabricating a semiconductor device according to claim 24 , wherein, in said step (d), arsenic ion is implanted, and wherein, in said step (e), phosphorus ion is implanted.
28. A method of fabricating a semiconductor device according to claim 24 , wherein, in said steps (d) and (e), boron ions are implanted.
29. A method of fabricating a semiconductor device, comprising steps of:
(a) forming a gate electrode of a MISFET over a main surface of a first semiconductor region of a first conductivity type formed in a semiconductor body, wherein an element forming region is defined by a shallow groove isolation layer such that said shallow groove isolation layer is formed by a CMP method;
(b) after said step (a), implanting ions in said first semiconductor region to form a second semiconductor region of a second conductivity type opposite to said first conductivity type;
(c) after said step (b), forming a side wall spacer on a side surface of said gate electrode;
(d) after said step (c), implanting ions at a first position in said first semiconductor region to form a third semiconductor region of said second conductivity type;
(e) after said step (c), implanting ions at a second position deeper than said first region in said first semiconductor region to form a fourth semiconductor region of said second conductivity type; and
(f) after said steps (d) and (e), forming a cobalt silicide layer in said third semiconductor region,
wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said third semiconductor region is greater than an impurity concentration of said fourth semiconductor region.
30. A method of fabricating a semiconductor device according to claim 29 , wherein said MISFET is included in a static random access memory (SRAM).
31. A method of fabricating a semiconductor device according to claim 29 , wherein said MISFET is included in a dynamic random access memory (DRAM).
32. A method of fabricating a semiconductor device according to claim 29 , wherein, in said step (d), arsenic ion is implanted, and wherein, in said step (e), phosphorus ion is implanted.
33. A method of fabricating a semiconductor device according to claim 29 , wherein, in said steps (d) and (e), boron ions are implanted.