Semiconductor chip having pads with plural junctions for different assembly methods
View Patent ↗Development efficiency and mass production efficiency of a semiconductor chip (LSI) is improved, whereby the LSI on which an integrated circuit is formed has plural pad parts connecting the integrated circuit with an external circuit. The pad part is provided with a first junction consisting of a window formed in the protective film and the pad exposed from the window, and a second junction consisting of a window formed in the protective film and a bump deposited on the pad exposed from the window. When it is required that the LSI is to be connected with an external circuit by wire bonding, the first junction is connected with the external circuit usina a wire. When it is required to connect the LSI with an external circuit by the TAB method or the COG method, the second junction is directly connected to the external circuit.
1. A semiconductor device comprising:
a semiconductor chip;
a plurality of conductive patterns formed on a top surface of the semiconductor chip, each of the plurality of conductive patterns includes a first connection area and a second connection area;
a protective film which covers the top surface of the semiconductor chip and the conductive patterns, wherein each of the first connection areas is exposed from respective first openings formed in the protective film, and each of the second connection areas is exposed from respective second openings formed in the protective film; and
a plurality of bumps formed on each of the second connection areas,
wherein each of the first connection areas has a configuration suitable for a wire connection, and
wherein at least one of the plurality of conductive patterns also includes a third connection area exposed from a third opening in the protective film so that the second and third connection areas of the at least one of the plurality of conductive patterns are formed to one first connection area, and a bump is formed on the third connection area.
2. The semiconductor device according to claim 1 , further comprising a plurality of conductive films each of which is disposed between one of bumps and one of the conductive patterns.
3. The semiconductor device according to claim 1 , wherein the top surface of the semiconductor chip includes a central area, and a peripheral area which surrounds the central area, and wherein each of the first connection areas is located in the central area and each of the second connection areas is located in the peripheral area.
4. The semiconductor device according to claim 1 , wherein the semiconductor chip has four sides, and wherein the first connection areas are located along the four sides of the semiconductor chip.
5. The semiconductor device according to claim 1 , wherein the bumps comprise solder.
6. The semiconductor device according to claim 1 , wherein the second connection areas are configured as tape automated bonding (TAB) junctions.
7. The semiconductor device according to claim 1 , wherein the second connection areas are configured as chip on glass (COG) bonding junctions.
8. The semiconductor device of claim 1 , further comprising a plurality of devices connected to the plurality of conductive patterns through the second and third connection areas, wherein different ones of the devices are respectively connected to the second opening and the third opening of the at least one of the plurality of conductive patterns.