Semiconductor chip having pads with plural junctions for different assembly methods
View Patent ↗Development efficiency and mass production efficiency of a semiconductor chip (LSI) is improved, whereby the LSI on which an integrated circuit is formed has plural pad parts connecting the integrated circuit with an external circuit. The pad part is provided with a first junction consisting of a window formed in the protective film and the pad exposed from the window, and a second junction consisting of a window formed in the protective film and a bump deposited on the pad exposed from the window. When it is required that the LSI is to be connected with an external circuit by wire bonding, the first junction is connected with the external circuit using a wire. When it is required to connect the LSI with an external circuit by the TAB method or the COG method, the second junction is directly connected to the external circuit.
1. A semiconductor device comprising:
a semiconductor chip;
a plurality of conductive patterns formed on a top surface of the semiconductor chip, each of which includes a first connection area and a second connection area, a first of the conductive patterns also including an additional second connection area;
a protective film which covers the top surface of the semiconductor chip and the conductive patterns, wherein each of the first connection areas is exposed from respective first openings formed in the protective film, and each of the second connection areas is exposed from respective second openings formed in the protective film;
conductive bump connections on the second connection areas including the additional second connection area, within the respective second openings; and
a wire connection electrically connected to the first connection area of the first of the conductive patterns.
2. The semiconductor device according to claim 1 , further comprising:
a first device mounted on the protective film and electrically connected to the second connection area of the first of the conductive patterns by a respective one of the conductive bump connections; and
a second device mounted on the protective film and electrically connected to the additional second connection area of the first of the conductive patterns by another respective one of the conductive bump connections.
3. The semiconductor device according to claim 2 , wherein the first and second devices are capacitors.
4. The semiconductor device according to claim 1 , wherein the wire connection is electrically connected to an external device.
5. The semiconductor device according to claim 1 , wherein the conductive bump connections comprise solder.
6. The semiconductor device according to claim 1 , wherein the second connection areas are configured as tape automated bonding (TAB) junctions.
7. The semiconductor device according to claim 1 , wherein the second connection areas are configured as chip on glass (COG) bonding junctions.
8. A semiconductor device comprising:
a semiconductor chip;
a plurality of conductive patterns formed on a top surface of the semiconductor chip, each of which includes a first connection area and a second connection area, a first of the conductive patterns also including an additional second connection area;
a protective film which covers the top surface of the semiconductor chip and the conductive patterns, wherein each of the first connection areas is exposed from respective first openings formed in the protective film, and each of the second connection areas is exposed from respective second openings formed in the protective film;
a first device mounted on the protective film and electrically connected to the second connection area of the first of the conductive patterns by a bump connection; and
a second device mounted on the protective film and electrically connected to the additional second connection area of the first of the conductive patterns by another bump connection,
wherein the first connection area of the first of the conductive patterns is electrically connected to an external device by a wire connection.
9. The semiconductor device according to claim 8 , wherein the second openings are provided with conductive material that is disposed therein on the conductive patterns and that projects from the second openings.
10. The semiconductor device according to claim 9 , wherein the conductive material comprises solder.
11. The semiconductor device according to claim 8 , wherein the top surface of the semiconductor chip includes a central area, and a peripheral area which surrounds the central area, and wherein each of the first connection areas is located in the peripheral area and each of the second connection areas is located in the central area.
12. The semiconductor device according to claim 8 , wherein the semiconductor chip has four sides, and wherein the first connection areas are located along the four sides of the semiconductor chip.
13. The semiconductor device according to claim 8 , wherein the second connection areas are configured as tape automated bonding (TAB) junctions.
14. The semiconductor device according to claim 8 , wherein the second connection areas are configured as chip on glass (COG) bonding junctions.
15. The semiconductor device according to claim 8 , wherein the first and second devices are capacitors.