Pulse width modulation circuit with multiphase clock

1. A pulse width modulation circuit, comprising:

a multiphase clock generation section generating a multiphase clock signal according to a reference clock; and

a pulse width modulation signal generation section generating a pulse width modulation signal according to input data and the multiphase clock signal generated by the multiphase clock generation section, by selecting an arbitrary clock signal from the multiphase clock signal in accordance with said input data,

wherein the multiphase clock generation section comprises a phase lock loop circuit and generates the multiphase clock signal by phase-interpolating an intermediate clock signal generated by the phase lock loop circuit,

wherein the pulse width modulation signal generation section comprises:

a clock selection circuit selecting the arbitrary clock signal from the multiphase clock signal generated by the multiphase clock generation section according to the input data; and

a pulse width modulation signal generation circuit generating a pulse width modulation signal according to the clock signal selected by the clock selection circuit,

wherein the clock selection circuit includes a first decoder decoding part of input data, a second decoder decoding another part of the input data, a first selector selecting a plurality of clock signals from the multiphase clock signal according to the data decoded by the first decoder, and a second selector selecting an arbitrary clock signal from the plurality of clock signals selected by the first selector according to the data decoded by the second decoder.

2. The pulse width modulation circuit of claim 1 , wherein the multiphase clock generation section comprises a phase interpolation circuit in a subsequent stage of a voltage controlled oscillator included in the phase lock loop circuit, and an output signal of the phase interpolation circuit is output as a multiphase clock signal.

3. The pulse width modulation circuit of claim 2 , wherein the phase lock loop circuit feeds back an arbitrary clock signal contained in the multiphase clock signal output from the phase interpolation circuit.

4. The pulse width modulation circuit of claim 1 , wherein the pulse width modulation signal generation section performs interleave control.

5. The pulse width modulation circuit of claim 1 , further comprising:

a synchronous position detection section receiving the multiphase clock signal generated by the multiphase clock generation section and a horizontal synchronous signal, and detecting a clock synchronous position with the horizontal synchronous signal from a plurality of clocks contained in the multiphase clock signal; and

a signal processing section converting the input data into rise information and fall information of a pulse width modulation signal according to the clock synchronous position detected by the synchronous position detection section, and outputting it as input data to the multiphase clock selection circuit.

6. The pulse width modulation circuit of claim 1 , wherein the pulse width modulation signal comprises a signal for modulating a laser output.

7. The pulse width modulation circuit of claim 1 , further comprising:

a synchronous position detection section receiving the multiphase clock signal generated by the multiphase clock generation section and a horizontal synchronous signal, and detecting a clock synchronous with the horizontal synchronous signal from a plurality of clocks contained in the multiphase clock signal.

8. The pulse width modulation circuit of claim 7 , further comprising:

a signal processing section converting the input data into rise information and fall information of a pulse width modulation signal according to a synchronous position detected by the synchronous position detection section, and outputting it as input data to the multiphase clock selection circuit.

9. A pulse width modulation circuit, comprising:

a multiphase clock generation section generating multiphase clock signals according to a reference clock;

a pulse width modulation signal generation section generating a pulse width modulation signal according to input data and the multiphase clock signals generated by the multiphase clock generation section; and

a synchronous position detection section receiving the multiphase clock signals generated by the multiphase clock generation section and a horizontal synchronous signal, and detecting a clock synchronous with the horizontal synchronous signal from a plurality of clocks contained in the multiphase clock signals,

wherein the multiphase clock generation section comprises a phase lock loop circuit and generates the multiphase clock signals by phase-interpolating an intermediate clock signal generated by the phase lock loop circuit.

10. The pulse width modulation circuit of claim 9 , wherein the multiphase clock generation section comprises a phase interpolation circuit in a subsequent stage of a voltage controlled oscillator included in the phase lock loop circuit, and an output signal of the phase interpolation circuit is output as multiphase clock signals.

11. The pulse width modulation circuit of claim 10 , wherein the phase lock loop circuit feeds back an arbitrary clock signal contained in the multiphase clock signals output from the phase interpolation circuit.

12. The pulse width modulation circuit of claim 9 , wherein the pulse width modulation signal generation section comprises:

a clock selection circuit selecting the arbitrary clock signal from the multiphase clock signals generated by the multiphase clock generation section according to the input data; and

a pulse width modulation signal generation circuit generating a pulse width modulation signal according to the clock signal selected by the clock selection circuit,

wherein the clock selection circuit includes a first decoder decoding part of input data, a second decoder decoding another part of the input data, a first selector selecting a plurality of clock signals from the multiphase clock signals according to the data decoded by the first decoder, and a second selector selecting an arbitrary clock signal from the plurality of clock signals selected by the first selector according to the data decoded by the second decoder.

13. The pulse width modulation circuit of claim 12 , wherein the pulse width modulation signal generation section performs interleave control.

14. The pulse width modulation circuit of claim 8 , further comprising:

a signal processing section converting the input data into rise information and fall information of a pulse width modulation signal according to a synchronous position detected by the synchronous position detection section, and outputting it as input data to the multiphase clock selection circuit.

15. The pulse width modulation circuit of claim 9 , wherein the pulse width modulation signal comprises a signal for modulating a laser output.

16. The pulse width modulation circuit of claim 1 , wherein the multiphase clock generation section comprises a phase interpolation circuit in a subsequent stage of a voltage controlled oscillator included in the phase lock loop circuit.

17. The pulse width modulation circuit of claim 16 , wherein an output signal of the phase interpolation circuit is output as a multiphase clock signal.

18. The pulse width modulation circuit of claim 9 , wherein the pulse width modulation signal generation section further comprises a pulse width modulation signal generation circuit generating a pulse width modulation signal according to the clock signal selected by the clock selection circuit.

19. The pulse width modulation circuit of claim 18 , wherein the clock selection circuit comprises:

a first decoder decoding part of input data;

a second decoder decoding another part of input data;

a first selector selecting a plurality of clock signals from the multiphase clock signal according to the data decoded by the first decoder; and

a second selector selecting an arbitrary clock signal from the plurality of clock signals selected by the first selector according to the data decoded by the second decoder.