Single transistor memory cell with reduced programming voltages
View Patent ↗A transistor fabrication method includes forming an electrode overlying a channel of a semiconductor on insulator (SOI) substrate. Source/drain structures are formed in the substrate on either side of the channel. The source/drain structures include a layer of a second semiconductor over a first semiconductor. The first and second semiconductors have different bandgaps. The second semiconductor extends under the gate electrode. The source/drain structures may be formed by doping the source/drain regions and etching the doped regions selectively to form voids. A film of the second semiconductor is then grown epitaxially to fill the void. A film of the first semiconductor may be grown to line the void before growing the second semiconductor. Alternatively, the second semiconductor is a continuous layer that extends through the channel body. A capping layer of the first semiconductor may lie over the second semiconductor in this embodiment.
1. A semiconductor fabrication process, comprising:
forming a gate stack including a gate electrode overlying a gate dielectric overlying a channel body of a semiconductor substrate, the channel body overlying a buried dielectric layer;
forming source/drain structures in source/drain regions of the substrate disposed on either side of the channel body, said forming of the source/drain structures including forming, in the source/drain regions, a layer of a second semiconductor material overlying a first semiconductor material, wherein a bandgap of the second material is different than a bandgap of the first material;
forming a capping layer comprising the first semiconductor material overlying the layer of the second semiconductor material; and
using the gate stack as a mask, patterning the capping layer and the layer of the second semiconductor material to form a two-dimensional migration barrier for liming vertical and lateral migration of majority carriers in the channel body.
2. The process of claim 1 , wherein forming the source/drain regions includes:
implanting the source/drain regions with an impurity species to form doped regions having an impurity concentration exceeding an impurity concentration of the channel body;
etching the doped regions selectively to form voids;
filling the voids with the second semiconductor material.
3. The method of claim 2 , wherein filling the voids comprises lining the voids with a first film and forming a second film on the first film wherein the first film comprises the first semiconductor material and the second comprises the second semiconductor material.
4. The method of claim 3 , wherein the channel body comprises silicon and the first film comprises silicon.
5. The method of claim 4 , wherein the channel body is p-type silicon and the first film is n-type silicon.
6. The method of claim 5 , wherein the second film heavily doped n-type silicon germanium.
7. The method of claim 3 , wherein the first film comprises silicon germanium and the second film comprises silicon.
8. The method of claim 1 , wherein the layer of the second semiconductor material comprises a continuous layer extending from a first source/drain region, through the channel body, to a second channel region.
9. The method of claim 8 , wherein the first semiconductor material and the capping layer are silicon and further wherein the second semiconductor layer comprises silicon germanium.
10. A semiconductor fabrication method, comprising:
forming a gate stack including a gate electrode overlying a gate dielectric overlying a channel body of a semiconductor layer overlying a buried oxide layer, wherein the semiconductor layer comprises a first semiconductor material;
forming source/drain structures in source/drain regions of the semiconductor substrate laterally disposed on either side of the channel body, wherein the source/drain structures include a layer of a second semiconductor material overlying the first semiconductor material;
wherein the layer of the second semiconductor material extends into the channel body underlying the gate electrode;
wherein the second semiconductor material has a narrower band gap than the first semiconductor material; and
forming a capping layer comprising the first semiconductor material overlying the layer of the second semiconductor material such that the layer of the second semiconductor material creates a potential well for majority carriers in the channel body.
11. The method of claim 10 , wherein the layer of the second semiconductor material is a continuous layer extending from a first source/drain region through the channel body to a second source/drain region.
12. The method of claim 10 , wherein forming the source/drain structures comprises:
creating heavily doped areas in the source/drain regions;
etching the heavily doped areas to create voids, wherein the voids extend under a portion of the gate electrode;
growing a first film of the first semiconductor material to line the voids and growing a second film of the second semiconductor material on the first film.