Recovering bit lines in a memory array after stopped clock operation
View Patent ↗In one embodiment, an apparatus comprises a plurality of memory cells; first and second bit lines coupled to the plurality of memory cells; a first and second bit line precharge circuits coupled to the first and second bit lines; and a control circuit coupled to the first and second bit line precharge circuits. The first and second bit line precharge circuits are each configured to precharge the first bit line and the second bit line. The control circuit is coupled to receive an indication that one or more clocks are being restarted after a period of stopped clock operation, and is configured to activate both the first and second bit line precharge circuits responsive to the indication and independent of an operation to the memory that was interrupted by the period of stopped clock operation, if any.
1. An apparatus comprising:
a plurality of memory cells;
a first bit line coupled to the plurality of memory cells and a second bit line coupled to the plurality of memory cells;
a first bit line precharge circuit coupled to the first bit line and the second bit line, wherein the first bit line circuit is configured to precharge the first bit line and the second bit line;
a second bit line precharge circuit coupled to the first bit line and the second bit line, wherein the second bit line circuit is configured to precharge the first bit line and the second bit line; and
a control circuit coupled to the first bit line precharge circuit and the second bit line precharge circuit, wherein the control circuit is coupled to receive an indication that one or more clocks are being restarted after a period of stopped clock operation, and wherein the control circuit is configured to activate both the first bit line precharge circuit and the second bit line precharge circuit responsive to the indication and independent of an operation to the memory that was interrupted by the period of stopped clock operation, if any.
2. The apparatus as recited in claim 1 wherein the control circuit is configured to activate the first bit line precharge circuit and not activate the second bit line precharge circuit responsive to a read operation to one of the plurality of memory cells.
3. The apparatus as recited in claim 2 wherein the control circuit is configured to activate at least the second bit line precharge circuit responsive to a write operation to one of the plurality of memory cells.
4. The apparatus as recited in claim 3 wherein the control circuit is configured to activate both the first bit line precharge circuit and the second bit line precharge circuit responsive to the write operation.
5. An apparatus comprising:
a plurality of memory cells;
a first bit line coupled to the plurality of memory cells and a second bit line coupled to the plurality of memory cells;
a first bit line precharge circuit coupled to the first bit line and the second bit line, wherein the first bit line circuit is configured to precharge the first bit line and the second bit line responsive to a read operation to one of the plurality of memory cells;
a second bit line precharge circuit coupled to the first bit line and the second bit line, wherein the second bit line circuit is configured to precharge the first bit line and the second bit line; and
a control circuit coupled to the first bit line precharge circuit and the second bit line precharge circuit, wherein the control circuit is coupled to receive an indication that a period of stopped clock operation is ending, and wherein the control circuit is configured to activate at least the second bit line precharge circuit responsive to the indication and even if a read operation was in progress at a start of the period of stopped clock operation.
6. The apparatus as recited in claim 5 wherein the control circuit is also configured to activate the first bit line precharge circuit in response to the indication.
7. The apparatus as recited in claim 5 wherein the control circuit, responsive to a write operation to one of the plurality of memory cells, is configured to activate at least the second bit line precharge circuit.
8. The apparatus as recited in claim 7 wherein the control circuit is also configured to activate the first bit line precharge circuit responsive to the write operation.
9. The apparatus as recited in claim 5 wherein the control circuit is configured to activate only the first bit line precharge circuit responsive to a read operation.
10. A method comprising:
ending a period of stopped clock operation; and
activating both a first bit line precharge circuit and a second bit line precharge circuit to precharge a first bit line and a second bit line to which the first bit line precharge circuit is coupled and to which the second bit line precharge circuit is coupled responsive to the end of the period and independent of an operation that was interrupted at a start of the period of stopped clock operation, if any.
11. The method as recited in claim 10 further comprising:
performing a write operation to one of a plurality of memory cells to which the first bit line and the second bit line are coupled; and
activating at least the second bit line precharge circuit responsive to the write operation.
12. The method as recited in claim 11 further comprising activating the first bit line precharge circuit responsive to the write operation.
13. The method as recited in claim 10 further comprising:
performing a read operation to one of a plurality of memory cells to which the first bit line and the second bit line are coupled; and
activating the first bit line precharge circuit and not the second bit line precharge circuit responsive to the write operation.