Patent Assignment
Reel/Frame 022793/0565
Assignment of Assignor's Interest
Recorded: 2009-06-09
Pages: 12
Assignor
PA SEMI, INC.
Executed: 2009-05-08
Assignee
APPLE INC.
1 INFINITE LOOP, CUPERTINO, CALIFORNIA, 95014
Covered Properties
(78)
Integrated Circuit with Separate Supply Voltage for Memory That Is Different from Logic Circuit Supply Voltage
PCT:
PCT/US2006/026096 ↗
Non-Blocking Address Switch with Shallow Per Agent Queues
PCT:
PCT/US2006/031520 ↗
Partially Populated, Hierarchical Crossbar
PCT:
PCT/US2006/031521 ↗
Explicit Flow Control in a Gigabit/10 Gigabit Ethernet System
PCT:
PCT/US2006/033329 ↗
Unified Dma
PCT:
PCT/US2006/038081 ↗
Network Direct Memory Access
PCT:
PCT/US2007/018329 ↗
Buffer Minimization in Interface Controller
PCT:
PCT/US2008/065553 ↗
Latency Reduction for Cache Coherent Bus-Based Cache
PCT:
PCT/US2008/065977 ↗
Recovering Bit Lines in a Memory Array After Stopped Clock Operation
Integrated Circuit with Separate Supply Voltage for Memory That Is Different from Logic Circuit Supply Voltage
Rapid Supply Voltage Ramp Using Charged Capacitor and Switch
Operating an Integrated Circuit at a Minimum Supply Voltage
Fast Hit Override
Digital Phase Relationship Lock Loop
Partial Load/Store Forward Prediction
Misalignment Predictor
Segmented Interconnect for Connecting Multiple Agents in a System
Non-Blocking Address Switch with Shallow Per Agent Queues
Read Port Circuit for Register File
Register File
Explicit flow control in Gigabit/10 Gigabit Ethernet system
Application:
11/211,259 →
Publication:
US 2007/0047572
Channelized flow control
Application:
11/212,075 →
Publication:
US 2007/0047443
Partially Decoded Register Renamer
Combined Buffer for Snoop, Store Merging, Load Miss, and Writeback Operations
Voltage-Controlled Oscillator for Low-Voltage, Wide Frequency Range Operation
Checksum Calculation
Unified Dma
Ordering Rule and Fairness Implementation
Functional Dma Performing Operation on Dma Data and Writing Result of Operation
R and C Bit Update Handling
Digital Leakage Detector That Detects Transistor Leakage Current in an Integrated Circuit
Floating Point Status/Control Register Encodings for Speculative Register Field
Data Cache Block Zero Implementation
Retry Mechanism in Cache Coherent Communication Among Agents
Combined Multiplexor/Flop
Pulsed Flop with Scan Circuitry
Pulsed Flop with Embedded Logic
Digital Jitter Detector
Prefetch Unit
Resonance Limiter Circuits for an Integrated Circuit
Network Direct Memory Access
Managed Credit Update
L1 Cache Flush When Processor Is Entering Low Power Mode
Uncacheable load merging
Application:
11/545,825 →
Publication:
US 2008/0086594
Early Retirement of Store Operation Past Exception Reporting Pipeline Stage in Strongly Ordered Processor with Load/Store Queue Entry Retained Until Completion
Replay Reduction for Power Saving
Cache Used Both as Cache and Staging Buffer
Low Latency, Power-Down Safe Level Shifter
Functional Dma Performing Operation on Dma Data and Writing Result of Operation
Clock Gater with Test Features and Low Setup Time
Enqueue Event First-in, First-Out Buffer (Fifo)
Data Flow Control Within and Between Dma Channels
Dma Controller Configured to Process Control Descriptors and Transfer Descriptors
Program Counter (Pc) Trace
Oversampling-Based Scheme for Synchronous Interface Communication
Operating an Integrated Circuit at a Minimum Supply Voltage
Interface Controller That Has Flexible Configurability and Low Cost
Buffer Minimization in Interface Controller
Efficient Encoding for Detecting Load Dependency on Store with Misalignment
Latency Reduction for Cache Coherent Bus-Based Cache
Converting Victim Writeback to a Fill
Store Handling in a Processor
Combined Single Error Correction/Device Kill Detection Code
Fast Static Rotator/Shifter with Non Two's Complemented Decode and Fast Mask Generation
Static 4:2 Compressor with Fast Sum and Carryout
Application:
11/760,547 →
Publication:
US 2009/0063609
Fast Modular Zero Sum and Ones Sum Determination
Memory Controller with Loopback Test Interface
Segmented Interconnect for Connecting Multiple Agents in a System
Integrated Circuit with Separate Supply Voltage for Memory That Is Different from Logic Circuit Supply Voltage
Partial Load/Store Forward Prediction
Non-Blocking Address Switch with Shallow Per Agent Queues
Replaying Memory Operation Assigned a Load/Store Buffer Entry Occupied by Store Operation Processed Beyond Exception Reporting Stage and Retired from Scheduler
Integrated Circuit with Separate Supply Voltage for Memory That Is Different from Logic Circuit Supply Voltage
Digital Phase Relationship Lock Loop
Prefetch Unit
Retry Mechanism
Flywheel: Circuit to prevent package resonance
Application:
60/798,084 →
Oversampling-Based Scheme for Synchronous Interface Communication
Application:
60/889,141 →
Related Assignments
(15)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jul 1, 2005
From: VON KAENEL, VINCENT R.
To: P.A. SEMI, INC.
Reel/Frame 016730/0341 →
Assignment of Assignor's Interest
Jul 1, 2005
From: DOBBERPUHL, DANIEL W.; VON KAENEL, VINCENT R.
To: P.A. SEMI, INC.
Reel/Frame 016755/0698 →
Assignment of Assignor's Interest
Jul 1, 2005
From: CAMPBELL, BRIAN J.; VON KAENEL, VINCENT R.; MURRAY, DANIEL C.; SCOTT, GREGORY S.
To: P.A. SEMI, INC.
Reel/Frame 016756/0742 →
Assignment of Assignor's Interest
Jul 1, 2005
From: CAMPBELL, BRIAN J.
To: P.A. SEMI, INC.
Reel/Frame 016755/0570 →
Assignment of Assignor's Interest
Jul 1, 2005
From: CAMPBELL, BRIAN J.
To: P.A. SEMI, INC.
Reel/Frame 016755/0575 →
Assignment of Assignor's Interest
Jul 7, 2005
From: WANG, JAMES; CHEN, ZONGJIAN; KELLER, JAMES B.
To: P.A. SEMI, INC.
Reel/Frame 016767/0142 →
Assignment of Assignor's Interest
Aug 10, 2005
From: KADAMBI, SUDARSHAN; CHANG, PO-YUNG; HAO, ERIC
To: P.A. SEMI, INC.
Reel/Frame 016887/0840 →
Assignment of Assignor's Interest
Aug 10, 2005
From: YEH, TSE-YU; CHANG, PO-YUNG; HAO, ERIC
To: P.A. SEMI, INC.
Reel/Frame 016880/0684 →
Assignment of Assignor's Interest
Aug 11, 2005
From: SUBRAMANIAN, SRIDHAR P.; KELLER, JAMES B.; WADHAWAN, RUCHI; YIU, GEORGE KONG
To: P.A. SEMI, INC.
Reel/Frame 016886/0735 →
Assignment of Assignor's Interest
Aug 11, 2005
From: SUBRAMANIAN, SRIDHAR P.; KELLER, JAMES B.; YIU, GEORGE KONG; WADHAWAN, RUCHI
To: P.A. SEMI, INC.
Reel/Frame 016886/0786 →
Assignment of Assignor's Interest
Aug 22, 2005
From: GOEL, RAJAT
To: P.A. SEMI, INC.
Reel/Frame 016913/0944 →
Assignment of Assignor's Interest
Aug 22, 2005
From: GOEL, RAJAT
To: P.A. SEMI, INC.
Reel/Frame 016915/0001 →
Assignment of Assignor's Interest
Aug 25, 2005
From: DESAI, SHAILENDRA S.; HAYTER, MARK D.
To: P.A. SEMI, INC.
Reel/Frame 016922/0134 →
Assignment of Assignor's Interest
Aug 25, 2005
From: DESAI, SHAILENDRA S.; HAYTER, MARK D.
To: P.A. SEMI, INC.
Reel/Frame 016933/0765 →
Assignment of Assignor's Interest
Aug 29, 2005
From: LIEN, WEI-HAN; YONG, JOHN K; SUNDAR, SHYAM; GOEL, RAJAT
To: P.A. SEMI, INC.
Reel/Frame 016934/0411 →