In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.
1. A processor comprising:
a prefetch unit comprising a prefetch buffer, wherein the prefetch buffer comprises a plurality of entries, and wherein each entry of the plurality of entries is configured to store data describing a different prefetch stream, and wherein the prefetch unit is programmable by software executed on the processor to limit a first number of the plurality of entries that are concurrently in use to less than a total number of the plurality of entries that are included in the prefetch buffer, and wherein the first number is greater than zero, wherein each of the plurality of entries includes a bit that is programmable by software to enable or disable the entry, and wherein the bit in each entry is written to program the first number; and
a data cache coupled to the prefetch unit, wherein the prefetch unit is configured to generate prefetch requests responsive to the prefetch streams to prefetch data in to the data cache.
2. The processor as recited in claim 1 wherein the first number is any integer greater than zero and less than or equal to the total number of the plurality of entries.
3. The processor as recited in claim 1 wherein a subset of the first number of the plurality of entries are reserved for software use by the software executed on the processor.
4. The processor as recited in claim 3 wherein each of the plurality of entries comprises a second bit that is written to reserve the entry for software use.
5. The processor as recited in claim 1 wherein each of the prefetch streams is either software initiated via execution by the processor of a dedicated prefetch instruction defined in the instruction set architecture implemented by the processor to cause a prefetch operation or hardware initiated via detection of a data cache miss by one or more load/store memory operations.
6. A processor comprising:
a prefetch unit comprising a prefetch buffer, wherein the prefetch buffer comprises a plurality of entries, and wherein each entry of the plurality of entries is configured to store data describing a different prefetch stream, and wherein the prefetch unit is programmable by software executed on the processor to allocate a first subset of the plurality of entries for software initiated prefetch streams and a remaining subset of the plurality of entries for hardware initiated prefetch streams; and
a data cache coupled to the prefetch unit, wherein the prefetch unit is configured to generate prefetch requests responsive to the prefetch streams to prefetch data in to the data cache.
7. The processor as recited in claim 6 wherein the first subset comprises at least one entry, and wherein the remaining subset comprises at least one entry.
8. The processor as recited in claim 7 wherein each of the plurality of entries includes a bit that is programmable by software to include the entry in the first subset or the remaining subset.
9. The processor as recited in claim 8 wherein each of the plurality of entries comprises a second bit that is written enable or disable the use of the entry.
10. The processor as recited in claim 6 wherein a number of entries in the first subset is any integer greater than zero and less than or equal to a number of the plurality of entries.
11. A method comprising:
programming a prefetch unit in a processor, wherein the prefetch unit comprises a prefetch buffer, and wherein the prefetch buffer comprises a plurality of entries, and wherein each entry of the plurality of entries is configured to store data describing a different prefetch stream, wherein the programming limits a first number of the plurality of entries that are concurrently in use to less than a total number of the plurality of entries that are included in the prefetch buffer, and wherein the first number is greater than zero, and wherein each of the plurality of entries includes a bit that is programmable by software to enable or disable the entry, and wherein the bit in each entry is written to program the first number; and
the processor generating prefetch requests responsive to the prefetch streams to prefetch data into a data cache.
12. The method as recited in claim 11 wherein the first number is any integer greater than zero and less than or equal to the total number of the plurality of entries.
13. The method as recited in claim 11 further comprising reserving a subset of the first number of the plurality of entries for software use, the reserving performed by software executed on the processor.
14. The method as recited in claim 13 wherein each of the plurality of entries comprises a second bit that is written to reserve the entry for software use.
15. A method comprising
programming a prefetch unit in a processor, wherein the prefetch unit comprises a prefetch buffer, and wherein the prefetch buffer comprises a plurality of entries, and wherein each entry of the plurality of entries is configured to store data describing a different prefetch stream, and wherein the programming allocates a first subset of the plurality of entries for software initiated prefetch streams and a remaining subset of the plurality of entries for hardware initiated prefetch streams; and
the processor generating prefetch requests responsive to the prefetch streams to prefetch data into a data cache.
16. The method as recited in claim 15 wherein the first subset comprises at least one entry, and wherein the remaining subset comprises at least one entry.
17. The method as recited in claim 16 further comprising programming wherein each of the plurality of entries to include the entry in the first subset or the remaining subset.
18. The method as recited in claim 15 wherein a number of entries in the first subset is any integer greater than zero and less than or equal to a number of the plurality of entries.