Data cache block zero implementation

1. A processor comprising:

a core configured to execute a data cache block write instruction; and

an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate;

wherein the core is configured to transmit a request to the interface unit in response to the data cache block write instruction, and wherein the interface unit is configured to issue a first transaction on the interconnect if the request is speculative, and wherein the interface unit is configured to issue a second transaction on the interconnect if the request is non-speculative, and wherein the second transaction is different from the first transaction, and wherein the first transaction is a probe, and wherein the interface unit is configured to record a state of a block affected by the data cache block write instruction in one or more caching agents as indicated by a probe response corresponding to the probe.

2. The processor as recited in claim 1 wherein the second transaction is an invalidate.

3. The processor as recited in claim 1 wherein the core is configured to reissue the request if the request is speculative.

4. The processor as recited in claim 3 wherein the interface unit is configured to monitor the address affected by the data cache block write instruction using the recorded state and a coherency protocol on the interconnect.

5. The processor as recited in claim 4 wherein the core is configured to reissue the request, and wherein the interface unit is configured to return an indication of complete for the request without transmitting a transaction on the interconnect if the request is non-speculative and the recorded state indicates that the block is invalid in the one or more caching agents.

6. The processor as recited in claim 1 wherein the interface unit comprises a request buffer, and wherein the interface unit is configured to allocate an entry in the request buffer to track the state, and wherein the interface unit is configured to compare an address of the request to addresses in the buffer to determine if the request has previously been received.

7. The processor as recited in claim 1 wherein the core comprises a load/store unit including a load/store queue, and wherein the load/store unit is configured to allocate an entry in the load/store queue for the data cache block write instruction, and wherein the load/store unit is configured to transmit the request from the entry.

8. The processor as recited in claim 1 wherein the data cache block write instruction comprises a data cache block zero instruction.

9. A system comprising:

an interconnect;

a processor coupled to the interconnect and configured to execute a data cache block write instruction, wherein the processor is configured to issue a first transaction on the interconnect if the data cache block write instruction is speculative, and wherein the processor is configured to issue a second transaction on the interconnect if the data cache block write instruction is non-speculative, and wherein the second transaction is different from the first transaction; and

one or more caching agents coupled to the interconnect; and

wherein the first transaction is a probe, and wherein the processor is configured to record a state of a block affected by the data cache block write instruction in the one or more caching agents as indicated by a probe response corresponding to the probe.

10. The system as recited in claim 9 wherein the second transaction is an invalidate.

11. The system as recited in claim 9 wherein the processor is configured to monitor the address affected by the data cache block write instruction using the recorded state and a coherency protocol on the interconnect.

12. The system as recited in claim 11 wherein the processor is configured to complete the data cache block write instruction without transmitting another transaction on the interconnect if the data cache block write instruction is non-speculative and the recorded state indicates that the block is invalid in the one or more caching agents.

13. The system as recited in claim 9 wherein the one or more caching agents comprise a second processor.

14. The system as recited in claim 9 wherein the one or more caching agents comprise a second level cache.

15. A method comprising:

executing a data cache block write instruction in a processor;

determining whether or not the data cache block write instruction is speculative;

selecting a selected transaction to be issued, the selecting between a probe and a second transaction different from the probe, and the selecting dependent on whether or not the data cache block write instruction is speculative;

issuing the selected transaction on an interconnect to which the processor is coupled; and

recording a state of a block affected by the data cache block write instruction in one or more caching agents as indicated by a probe response corresponding to the probe.

16. The method as recited in claim 15 wherein the second transaction is an invalidate.

17. The method as recited in claim 15 further comprising:

monitoring the address affected by the data cache block write instruction using the recorded state and a coherency protocol on the interconnect; and

completing the data cache block write instruction without transmitting another transaction on the interconnect if the data cache block write instruction is non-speculative and the recorded state indicates that the block is invalid in the one or more caching agents.