Preamorphization to minimize void formation
View Patent ↗Methods are described for eliminating void formation during the fabrication of and/or operation of memory cells/devices. According to one aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the opening, preamorphization of the metal using preamorphization implants, and formation of a conductivity facilitating layer. According to another aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the opening, preamorphization of the metal using a contact with a plasma, and formation of a conductivity facilitating layer.
1. A method for preventing void formation in a memory cell, comprising:
depositing a metal into an opening of a semiconductor substrate;
preamorphizing a portion of the metal using a preamorphization implantation with an implant species;
forming a conductivity facilitating layer over the amorphized metal;
forming an active layer over the conductivity facilitating layer and a top electrode over the active layer, and a thin barrier layer between the active layer and the top electrode; and
patterning the memory cell.
2. The method of claim 1 , wherein the metal comprises at least one of copper, alloys of copper, compounds of copper and mixtures thereof.
3. The method of claim 1 , wherein the implant species is selected from the group consisting of argon, helium, xenon, germanium, sulfur, selenium, tellurium, polonium, and carbon.
4. The method of claim 1 , wherein the preamorphization implantation is performed with an implant energy from about 0.1 keV to about 500 keV.
5. The method of claim 1 , wherein the implant species are implanted at a dose ranging from about 1×10 12 atoms per cm 2 to about 1×10 17 atoms per cm 2 .
6. The method of claim 1 , wherein the metal is implanted to a thickness ranging from about 10 nm to about 100 nm.
7. The method of claim 1 , wherein the preamorphization implantation is carried out at an implantation angle greater than zero degrees.
8. The method of claim 1 , wherein the conductivity facilitating layer comprises copper sulfide.
9. The method of claim 1 , wherein the active layer comprises an organic semiconductor or an inorganic semiconductor material.
10. The method of claim 1 , wherein the thin barrier layer comprises titanium or titanium nitride.
11. A method for preventing void formation in a memory cell, comprising:
depositing a metal into an opening of a semiconductor substrate;
preamorphizing a portion of the metal by contacting the metal with a plasma using a reactive ion etch tool, the plasma comprises at least one selected from the group consisting of germanium, sulfur, selenium, tellurium, polonium, and carbon;
forming a conductivity facilitating layer over the amorphized metal;
forming an active layer over the conductivity facilitating layer and a top electrode over the active layer; and
patterning the memory cell.
12. The method of claim 11 , wherein the plasma comprises sulfur.
13. The method of claim 11 , wherein the metal comprises at least one of copper, alloys of copper, compounds of copper and mixtures thereof.
14. The method of claim 11 , wherein the plasma has a density from about 1×10 9 ions per cm 3 to about 1×10 13 ions per cm 3 .
15. The method of claim 11 , wherein the plasma is energized to a RF power from about 10 to about 600 W.
16. The method of claim 11 , wherein the plasma is adjusted to a bias voltage from about 50 V to about 500 V.
17. The method as in claim 11 , wherein the plasma is implanted at an implant energy from about 0.1 KeV to about 50 KeV.
18. The method of claim 11 , wherein the conductivity facilitating layer comprises one or more of copper sulfide, copper rich copper sulfide, copper oxide, copper selenide, copper telluride, manganese oxide, titanium oxide, indium oxide, silver sulfide, gold sulfide iron oxide, cobalt arsenide, and nickel arsenide.
19. The method of claim 11 , further comprising a thin barrier layer between the active layer and the top electrode.
20. A method for preventing void formation in a memory cell, comprising:
depositing a metal into an opening of a semiconductor substrate;
preamorphizing a portion of the metal by contacting the metal with a plasma using a reactive ion etch tool, the plasma comprising at least one selected from the group consisting of germanium, sulfur, selenium, tellurium, polonium, and carbon;
forming a conductivity facilitating layer over the amorphized metal; and patterning the memory cell.