Optimization of memory accesses in a circuit design
View Patent ↗Methods and apparatus for optimizing memory accesses in a circuit design are described. According to one embodiment, a method comprises identifying a subset of variables from a multi-variable memory space that are accessed by a plurality of loops, storing the subset of variables in a separately accessible memory space, and accessing one of the stored subset of variables to recover a stored value of the one of the stored subset of variables for use by at least one of the plurality of loops during synthesis. According to another embodiment, a method comprises identifying at least a first loop and a second loop, determining whether a dependency exists between the first loop and the second loop, and merging the first loop and the second loop into a single merged loop, wherein the merging comprises mapping a plurality of memory accesses from the first loop to a sliding window.
1. In a behavioral synthesis tool used to design a hardware circuit, a method comprising:
identifying a subset of variables from a multi-variable memory space that are accessed by a plurality of loops, wherein identifying a subset of variables comprises determining that a plurality of memory accesses from inside one of the plurality of loops comprises linear loop expressions;
storing the subset of variables in a separately accessible memory space, wherein storing the subset of variables comprises constructing a sliding window, wherein the sliding window has a size determined at least in part by a value corresponding to how many variables the subset of variables comprises; and
accessing one of the stored subset of variables to recover a stored value of the one of the stored subset of variables for use by at least one of the plurality of loops during synthesis.
2. The method of claim 1 , wherein the sliding window is mapped to a shift register.
3. The method of claim 1 , wherein the sliding window is mapped to a cyclic buffer.
4. The method of claim 1 , wherein the sliding window is mapped to a message channel.
5. The method of claim 1 , wherein the sliding window is represented as a C++ class.
6. The method of claim 1 , wherein each of the subset of variables comprises an array and the sliding window is a subset of a multi-dimensional array.
7. The method of claim 6 , wherein each of the subset of variables comprises a line buffer, the line buffer comprising a plurality of pixels, and the multi-dimensional array comprises a frame of video from a video data stream.
8. The method of claim 6 , wherein the multi-dimensional array models video data in a video filter.
9. The method of claim 1 , wherein the subset of variables are shared between a plurality of processes and the sliding window is synchronized between the plurality of processes.
10. The method of claim 1 , further comprising unrolling at least one of the plurality of loops.
11. The method of claim 1 , further comprising pipelining a sub-plurality of the plurality of loops.
12. The method of claim 1 , further comprising reducing a plurality of accesses to a memory to one access per clock cycle.
13. A computer-readable medium having stored thereon computer-executable instructions for performing the method of claim 1 .
14. The method of claim 1 , wherein identifying a subset of variables further comprises determining that a plurality of memory accesses from outside the one of the plurality of loops comprises constant indexes.