Method for fabricating CMOS image sensor
A method for fabricating a CMOS image sensor is disclosed, to minimize the leakage current and to improve the yield, which includes the steps of preparing a semiconductor substrate including a peripheral circuit and a pixel array, wherein the pixel array is comprised of a photodiode and a readout circuit; defining an active area and a field area in the semiconductor substrate; forming a field oxide layer in the field area of the semiconductor substrate; forming gate electrodes in the peripheral circuit and the readout circuit of the pixel array; forming a photodiode in a photodiode portion of the pixel array; forming source and drain junctions at both sides of the gate electrode in the semiconductor substrate of the active area; forming a salicide prevention layer in the semiconductor substrate of the pixel array; and forming salicide layers in the surface of the gate electrode and the source and drain junctions in the peripheral circuit by using the salicide prevention layer as a mask.
1 . A method for fabricating a CMOS image sensor comprising:
preparing a semiconductor substrate including a peripheral circuit and a pixel array, wherein the pixel array is comprised of a photodiode and a readout circuit;
defining an active area and a field area in the semiconductor substrate;
forming a field oxide layer in the field area of the semiconductor substrate;
forming gate electrodes in the peripheral circuit and the readout circuit of the pixel array;
forming a photodiode in a photodiode portion of the pixel array;
forming source and drain junctions at both sides of the gate electrode in the semiconductor substrate of the active area;
forming a salicide prevention layer in the semiconductor substrate of the pixel array; and
forming salicide layers in the surface of the gate electrode and the source and drain junctions in the peripheral circuit by using the salicide prevention layer as a mask.
2 . The method of claim 1 , wherein the process for forming the salicide prevention layer includes the step of planarizing the salicide prevention layer to expose the upper surface of the gate electrode.
3 . The method of claim 2 , wherein the step of planarizing the salicide prevention layer is performed by CMP (Chemical Mechanical Polishing).
4 . The method of claim 1 , wherein the process for forming the salicide prevention layer includes the step of planarizing the salicide prevention layer not to expose the upper surface of the gate electrode.
5 . The method of claim 1 , wherein the process for forming the salicide layers corresponds to the process of forming the salicide prevention layer in the surface of the gate electrode and the source and drain junctions in the peripheral circuit.
6 . The method of claim 1 , wherein the process for forming the salicide layers corresponds to the process of forming the salicide layers in the surface of the gate electrode of the pixel array, in the surface of the gate electrode of the peripheral circuit, and in the surface of the source and drain junctions of the peripheral circuit.