Method of manufacturing a multi-workfunction gates for a CMOS circuit
View Patent ↗A method of manufacturing a device includes doping a low voltage threshold area and a high voltage threshold area. Gate structures are formed over the low voltage threshold and high voltage threshold areas while protecting the gate structure over the low voltage threshold area. A silicidation process is performed over the high voltage threshold area while the gate structure over the low voltage threshold area remains protected. Siliciding includes depositing metal on the gate of the high voltage threshold area and annealing the metal, the metal is deposited either by CVD or sputtering followed by anneal to fully suicide the gate structure of the high voltage threshold area. The metal, preferably cobalt or nickel is deposited to a thickness of approximately 500 Å, annealed for about 3 minutes at about 400° C.
1. A method of manufacturing a device, comprising:
doping a low voltage threshold area and a high voltage threshold area formed in a substrate;
forming gate structures over the low voltage threshold area and the high voltage threshold area;
protecting the gate structure over the low voltage threshold area; and
performing a silicidation process over the high voltage threshold area while the gate structure over the low voltage threshold area remains protected, wherein:
the silicidation process includes depositing a metal on the gate structure of the high voltage threshold area and annealing the metal,
the metal is deposited either by CVD or sputtering followed by anneal to fully silicide the gate structure of the high voltage threshold area, and
wherein the metal is cobalt or nickel deposited to a thickness of approximately 500 Å which is annealed for about 3 minutes at about 400° C.
2. The method of claim 1 , further comprising stripping a nitride cap from the gate structure of the high voltage threshold area prior to performing the silicidation process.
3. The method of claim 1 , further comprising depositing an oxidation layer over the substrate including the gate structure of the low voltage threshold area and the high voltage threshold area.
4. The method of claim 3 , further comprising planarizing the oxidation layer at least over the gate structures of the low voltage threshold area and the high voltage threshold area.
5. The method of claim 4 , wherein the planarizing is stopped on the nitride cap layer above the gate structures of the low voltage threshold area and the high voltage threshold area.
6. The method of claim 1 , wherein the protecting step comprises patterning a photoresist over the low voltage threshold area, and the patterning includes etching away a cap formed over the gate structure of the high voltage threshold area to expose the gate structure of the high voltage threshold area.
7. The method of claim 6 , further comprising etching the photoresist over the low voltage threshold area, leaving a nitride cap substantially intact to protect the gate structure of the low voltage threshold area during the silicidation process.
8. The method of claim 1 , further comprising fine-tuning a voltage threshold of the high threshold area by implanting a midgap workfunction gate material.
9. A method of manufacturing a device, comprising:
providing a substrate with a low voltage threshold area and a high voltage threshold area;
doping the low voltage threshold area and the high voltage threshold area with a dopant;
forming a gate structure over the low voltage threshold area and the high voltage threshold area which includes sidewalls and a cap;
performing an oxidation process to cover exposed areas of the substrate;
etching the cap of the gate structure of the high voltage threshold area to expose the gate structure of the high voltage threshold area; and
siliciding the gate structure of the high voltage threshold area while the gate structure of the low voltage threshold area remains protected, wherein:
the siliciding includes depositing a metal on the gate structure of the high voltage threshold area and annealing the metal,
the metal is deposited either by CVD or sputtering followed by anneal to fully silicide the gate structure of the high voltage threshold area, and
the metal is cobalt or nickel deposited to a thickness of approximately 500 Å which is annealed for about 3 minutes at about 400° C.
10. The method of claim 9 , wherein the protecting of the gate structure of the low voltage threshold area includes patterning a photoresist over the gate structure of the low voltage threshold area, including the oxide layer over the low voltage threshold area.
11. The method of claim 9 , wherein the high voltage threshold area and the low voltage threshold area include an nFET device or a pFET device.
12. The method of claim 11 , wherein the doping for the pFET device is one of P, As, and Sb and for the nFET device are one of B, In and BF 2 .
13. The method of claim 9 , further comprising fine-tuning a voltage threshold of the high threshold area by implanting a midgap workfunction gate material.